why does my Verilog adder-subtractor fail the addition here with 1 more than correct answer? - binary

Question

I wrote a 4-bit full-adder-subtractor, and my code managed to operate subtraction but failed operating addition with 1 more than the correct answer: 0101+0101=1011. Help!
Here's the full-adder-subtractor code:
module Add_sub(x,y,co,u,en);
input [3:0] x, y;
input en; // en=1: add; en=0:sub
output [3:0] u;
output co;
wire [3:1]carry;
FA M0(x[0], y[0], en, en, u[0], carry[1]);
FA M1(x[1], y[1], carry[1], en, u[1], carry[2]);
FA M2(x[2], y[2], carry[2], en, u[2], carry[3]);
FA M3(x[3], y[3], carry[3], en, u[3], co);
endmodule
module FA(x,y,cin,en,u,co);
input x, y, cin, en;
output u, co;
wire b = !x^en;
assign u = x^y^cin;
assign co = (b&y)|(b&cin)|(y&cin);
endmodule
Here's the testbench code:
`timescale 1ns/1ns
module testbench();
reg [3:0]x, y;
reg en;
wire[3:0]u;
wire co;
Add_sub tb(.x(x), .y(y), .co(co), .u(u), .en (en));
initial begin
$monitor ($time, "x=%b, y=%b, co=%b, u=%b, en=%b",x,y,co,u,en);
end
initial begin
#0 x=5; y=5; en=1; // add operation
#20 x=5; y=5; en=0; // sub operation
#20 x=8; y=1; en=1; // add operation
#20 x=8; y=1; en=0; // sub operation
#20 $stop;
end
endmodule
Here's the simulation Wave:

Answer 1

I re-wrote your code as following:
module Add_sub(x,y,co,u,en);
input [3:0] x, y;
input en; // en=1: add; en=0:sub
output [3:0] u;
output co;
wire [3:1]carry;
wire ci = ~en;
FA M0(x[0], y[0], ci, en, u[0], carry[1]);
FA M1(x[1], y[1], carry[1], en, u[1], carry[2]);
FA M2(x[2], y[2], carry[2], en, u[2], carry[3]);
FA M3(x[3], y[3], carry[3], en, u[3], co);
endmodule
module FA(x,y,cin,en,u,co);
input x, y, cin, en;
output u, co;
wire b = en ? y : (~y);
assign u = x^b^cin;
assign co = (b&x)|(b&cin)|(x&cin);
endmodule