addResource across multiple Chisel Modules while maintaining compile order - chisel

Question

Working with Chipyard, I have multiple Chisel modules that rely on blackbox SystemVerilog files.
These files share common package dependencies and Verilator's strict compile order compliance results in undefined packages. We are using the Chisel/FIRRTL generated file lists.
Let's assume the following example classes:
class ModX extends BlackBox {
addResource("packageA.sv")
addResource("packageB.sv")
addResource("ModX.sv")
}
class ModY extends BlackBox {
addResource("packageB.sv")
addResource("packageC.sv")
addResource("ModY.sv")
}
The following .f files are generated during the build with *.top.f being the focus of this issue:
firrtl_black_box_resource_files.harness.f
firrtl_black_box_resource_files.top.f
sim_files.f
It seems that FIRRTL enumerates the addResource list in reverse order, which can be accommodated by reversing the addResource order in the Chisel module.
Based on my experience, firrtl_black_box_resource_files.top.f would contain the following:
ModX.sv
packageA.sv
ModY.sv
packageC.sv
packageB.sv
I can tweak the order within the module and get the following:
packageA.sv
ModX.sv
packageB.sv
packageC.sv
ModY.sv
What I need, however, is to ensure that when redundant addResources are eliminated during elaboration, the "first" instance is kept, not the last instance. As a result of the above example, Verilator will fail compilation because packageB.sv has not been compiled before ModX.sv
Does anyone know of a work-around?