Why are the bits in this Verilog wire assigned as 'z'? - binary

Question

I am trying to create a multiplication module in Verilog for an ALU project.
When I pass test values to this modules, 0100101010011100 and 0100110000000000 and print these values with $display(), they appear normal. However, if I try to print one of my calculated values like p0-p15, it shows 16bits of z. I don't understand why this is happening, because it appears I am assigning {16{inputA[0]}} & inputB[15:0] which shows valid results when I print it out.
The only conclusion that I can come to is that I am either calling this module improperly, or assigning the values improperly.
Should I be using reg instead of wires for the 15 'p' variables?
module Product(inputA, inputB, Output);
input [15:0] inputA, inputB;
output [31:0] Output;
//calculate 16 subproducts
wire [15:0] p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15;
//assign p0[15:0] = {16{inputA[0]}} & inputB[15:0];
assign p0[15:0] = {16{inputA[0]}} & inputB[15:0];
assign p1[15:0] = {16{inputA[1]}} & inputB[15:0];
assign p2[15:0] = {16{inputA[2]}} & inputB[15:0];
assign p3[15:0] = {16{inputA[3]}} & inputB[15:0];
assign p4[15:0] = {16{inputA[4]}} & inputB[15:0];
assign p5[15:0] = {16{inputA[5]}} & inputB[15:0];
assign p6[15:0] = {16{inputA[6]}} & inputB[15:0];
assign p7[15:0] = {16{inputA[7]}} & inputB[15:0];
assign p8[15:0] = {16{inputA[8]}} & inputB[15:0];
assign p9[15:0] = {16{inputA[9]}} & inputB[15:0];
assign p10[15:0] = {16{inputA[10]}} & inputB[15:0];
assign p11[15:0] = {16{inputA[11]}} & inputB[15:0];
assign p12[15:0] = {16{inputA[12]}} & inputB[15:0];
assign p13[15:0] = {16{inputA[13]}} & inputB[15:0];
assign p14[15:0] = {16{inputA[14]}} & inputB[15:0];
assign p15[15:0] = {16{inputA[15]}} & inputB[15:0];
initial begin
$display("%b",inputA);
$display("%b",inputB);
$display("----------------");
$display("%b", {16{inputA[0]}} & inputB[15:0]);
$display("%b", {16{inputA[1]}} & inputB[15:0]);
$display("%b", {16{inputA[2]}} & inputB[15:0]);
$display("%b", {16{inputA[3]}} & inputB[15:0]);
$display("%b", {16{inputA[4]}} & inputB[15:0]);
$display("%b", {16{inputA[5]}} & inputB[15:0]);
$display("%b", {16{inputA[6]}} & inputB[15:0]);
$display("%b", {16{inputA[7]}} & inputB[15:0]);
$display("%b", {16{inputA[8]}} & inputB[15:0]);
$display("%b", {16{inputA[9]}} & inputB[15:0]);
$display("%b", {16{inputA[10]}} & inputB[15:0]);
$display("%b", {16{inputA[11]}} & inputB[15:0]);
$display("%b", {16{inputA[12]}} & inputB[15:0]);
$display("%b", {16{inputA[13]}} & inputB[15:0]);
$display("%b", {16{inputA[14]}} & inputB[15:0]);
$display("%b", {16{inputA[15]}} & inputB[15:0]);
$display("----------------");
$display("%b",p0);
$display("%b",p1);
$display("%b",p2);
$display("%b",p3);
$display("%b",p4);
$display("%b",p5);
$display("%b",p6);
$display("%b",p7);
$display("%b",p8);
$display("%b",p9);
$display("%b",p10);
$display("%b",p11);
$display("%b",p12);
$display("%b",p13);
$display("%b",p14);
$display("%b",p15);
$display("----------------");
end
wire [31:0] s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15;
assign s0[31:0] = p0 << 0;
assign s1[31:0] = p1 << 1;
assign s2[31:0] = p2 << 2;
assign s3[31:0] = p3 << 3;
assign s4[31:0] = p4 << 4;
assign s5[31:0] = p5 << 5;
assign s6[31:0] = p6 << 6;
assign s7[31:0] = p7 << 7;
assign s8[31:0] = p8 << 8;
assign s9[31:0] = p9 << 9;
assign s10[31:0] = p10 << 10;
assign s11[31:0] = p11 << 11;
assign s12[31:0] = p12 << 12;
assign s13[31:0] = p13 << 13;
assign s14[31:0] = p14 << 14;
assign s15[31:0] = p15 << 15;
end module
module testbench();
reg [4:0] i;
parameter n=16;
reg [15:0] inputA;
reg [15:0] inputB;
reg [4:0] opcode;
wire [31:0] out1;
wire [1:0] out2;
wire [15:0] a,b;
assign a =16'b0100_1010_1001_1100;
assign b =16'b0100_1100_0000_0000;
Product prod(a, b, out1);
endmodule

Answer 1

This is a time-0 race condition because you have not given enough time for the inputs to propagate to the outputs. Other simulators show non-z results. You can add a #1 before you display any of your signals.
In general simulation needs time to propagate all statements that happen concurrently.