Do all I-type MIPS instructions take the same number of cycles in a multi-cycle datapath? I know R-type have the same number of cycles.
Do all I-type MIPS instructions take the same number of cycles in a multi-cycle datapath?
No.
First, let's look at some of the instructions are included in the MIPS I-Type category: addi and lw. These are both I-Type instructions — with the identical 16-bit immediate and rs and rt fields. They are decoded using the same fields, which is why they are both considered I-Type instructions.
Ok, next, let's look at the multicycle processor. This is not a pipelined processor, though, generally speaking, it will have a cycle for each stage in an equivalent pipelined version.
While we would generally find a pipelined processor's performance superior at the same megahertz, one advantage of a multicycle processor implementation over a pipelined processor implementation is that "stages" that are not needed can be skipped (skipping a cycle is not viable in a pipelined processor because of the instruction execution overlap; whereas the multicycle processor does not overlap execution of instructions).
So, among IF, ID, EX, MEM, WB stages, addi does not require or make use of the MEM stage, and thus it would be silly not to skip that cycle, making addi a 4 cycle instruction.
However, lw, does require the MEM stage (so all the stages) hence it will be 1 cycle longer than addi.
Related
Why are registers A and B whose inputs are ReadData1 and ReadData2 of RegisterFile are necessary? Isn't it possible to use directly the values which are on ReadData1 and ReadData2 outputs of Register File?
Instruction Register is already loaded with an instruction, so the value of IR is fixed, which means that $rs, $rt, $rd reg numbers are obviously the same within a single instruction. Hence, there are always the same values on the ReadRegister1 and ReadRegister2 inputs of the Register File. So the values that are on RD1 and RD2 outputs are the same unless the corresponding registers inside RegisterFile are overwritten.
That means that A and B registers are necessary only for the instructions that require to have the values of $rs or $rd registers that were overwritten on previous cycle. Can anybody give me an example of such an instruction.
The general pattern is that during a clock cycle: at the start of the clock, some register(s) feed values to computational logic which feed values to (the same or other) register(s) by the end of the clock, so that it can start all over again for the next cycle.
In the single cycle datapath, the value in the PC starts the process of the cycle, and by the end of the cycle, the PC register is updated to repeat a new cycle with another value. Along the way, the register file is both consulted and also (potentially) updated. You may note that these A & B registers are not present in the single cycle datapath.
You are correct that those values do not change during the execution of any one single instruction on the multicycle datapath.
However, the multicycle processor uses multiple cycles to execute a single instruction (so that it can speed the clock). In order to support the successive cycles in that processor design, some internal registers are used — they capture the output of a prior cycle in order for a next cycle to do something different.
The problem with the multicycle datapath diagrams is that they don't make it clear what part of the processor runs in what cycles. Those A & B registers are there to support a cycle boundary, so the decode is happening in one cycle and the arithmetic/ALU in another cycle. (Without those registers, the processor would have to perform decode again in the subsequent cycle, which would decrease the clock rate and defeat the nature of the multicycle datapath.)
Boundaries are made much more clear in pipeline datapath diagrams. Search for "MIPS pipeline datapath". (Note that some pipeline datapath diagrams show registers between stages and others simply outline what's in what stage without showing those registers.) The large vertical bars are registers and they separate the pipeline stages. Of course, the pipeline processor executes all pipeline stages in parallel, though in theory, similar boundaries are applicable to the cycles in a multicycle processor. Note that the ID/EX pipeline register in the pipeline datapath serves the purpose of the A & B registers in the multicycle datapath.
I'm given stages of a clock cycle in a processor.
IF ID EX MEM WB
250ps 350ps 150ps 300ps 200ps
Now I'm being asked what is the total latency of a LW instruction in a pipelined instruction.
Here's what I know:
The clock cycle time in a pipelined version is 350ps because that's the longest instruction.
The clock cycle time in a non-pipelined version is 1250ps because that's the duration of all the instructions added together.
But how does the "latency of a LW instruction" relate to those times?
Ok I'm pretty sure I figured out the answer which is you take the longest duration of the stages which in this case is 350ps and you multiply it by the amount of stages, in this case 5.
So
350 * 5 = 1750ps
Yes, you are correct with your result. Here is the formula:
(Number of Instructions)(Longest Instruction Time with (Unit)) = Latency(Unit)
For a 32-bit MIPS, an R-type instruction looks like this:
Say that we expanded the MIPS instruction set to contain four times as many instructions. Would the opcode increase from 6-bits to 8-bits?
Some sources say that the opcode would increase, but many are saying that the opcode wouldn't increase.
I think that the opcode would increase since we now need a larger space to address more instructions.
In MIPS, an R type instruction is identified with opcode 0, and the operation is encoded in funct. So, on increasing the number of instructions to four times, funct should increase by 2 bits and not opcode
I am trying to write out MIPS binary code for machine instructions which have to do with floating-point registers. But while I can find the opcode for the floating-point instructions, I can't find out what numbers refer to which floating-point registers. My book and the Internet can tell me which number register I would use if I wanted to refer to $t1, but I can't find any information on how I would refer to $f1.
There are 32 floating point registers: $f0..$f31. But every floating point operation is done (in early MIPS processors) in separate processing unit, FPU (Floating point unit), so you can't access floating point registers with ordinary (integer) command. FPU registers for FPU commands and CPU registers for CPU commands.
There is a picture and transparent description
http://www.cim.mcgill.ca/~langer/273/12-coprocessors.pdf
All FPU commands are encoded as Coprocessor Instructions, for coprocessor 1 (CP1)
Check first and last pages of http://www.cs.sunysb.edu/~lw/spim/MIPSinstHex.pdf
Fields ft(5) fs(5) fd(5) are codes of registers (all are 5 bit wide). $f0 will be coded as 0; $f31 as 31 (dec) or 0x1f (hex). For double-register values (64-bit double format), only number of first register from register pair is recorded (only even regnumber is allowed: 0,2 ..30).
Detailed tables of opcodes are here: http://www.math.unipd.it/~sperduti/ARCHITETTURE-1/mips32.pdf (page A-73)
If a thirty-two bit word can represent a MIPS instruction. How can we tell if that instruction is of type R, J, or I?
I'm having a hard time understanding these concepts, I think the opcodes might be different?
Basically MIPS instructions have an opcode stored in the most significant 6 bits which specify the format of the following bits. In particular, R-type instructions always have an opcode of 000000 (with the instruction functionality then further specified by the 6 least significant bits.
MIPS Instruction Coding