Demuxer : Unconnected Wires / firrtl error - chisel

Question

I am trying to make a demuxer using Chisel but the code fails to compile and throw this error shown in the imgur link
[1] https://i.stack.imgur.com/oW0Rv.png)
class Demuxer extends Module {
val io = IO(new Bundle {
val datain = Input(UInt(8.W))
val dataout1 = Output(UInt(8.W))
val dataout2 = Output(UInt(8.W))
val dataout3 = Output(UInt(8.W))
val dataout4 = Output(UInt(8.W))
val dataout5 = Output(UInt(8.W))
val selector = Input((UInt(3.W)))
})
when(io.selector === 1.U){
io.dataout1 := io.datain
}.elsewhen(io.selector === 2.U){
io.dataout2 := io.datain
}.elsewhen(io.selector === 3.U){
io.dataout3 := io.datain
}.elsewhen(io.selector === 4.U){
io.dataout4 := io.datain
}.elsewhen(io.selector === 5.U){
io.dataout5 := io.datain
}.otherwise{
}
}
I read the wiki about unconnected element
https://www.chisel-lang.org/chisel3/docs/wiki-deprecated/unconnected-wires.html
If I use use io.outs <> DontCare on my IO, the code compiles but the generated verilog shorts my inputs to all the outputs, which is not the desired behaviour I want from this module. Can any one suggest I fix to this problem?
Thanks in advance

Answer 1

Chisel and the Scala FIRRTL Compiler require that all outputs are driven in all cases. This helps avoid bugs where a designer forgets to drive some port/wire/reg. The issue is that the code needs to set some default value (or use DontCare) for all of the module outputs.
When you set all the outputs to DontCare usually one of two things will happen:
The default connection will be 0.U.
The default connection will be some other legal value or connection.
(2) is what is happening here. When you write io.dataout1 := DontCare, you're indicating to the compiler that it can set this to anything. The compiler is then choosing to set this to io.dataout1 := io.datain (shorting the input to the output).
Instead of using DontCare you can use something explicit, e.g., 0.U will create a mux for each output. Doing this with one line looks like:
Seq(io.dataout1, io.dataout2, io.dataout3, io.dataout4, io.dataout5).foreach(
_ := 0.U
)