Chisel 3.4.2 syncmem and a black box. No memory replacement with --repl-seq-mem option - chisel

Question

I run MemtestInst code with --repl-seq-mem option. It has a black box and a SyncReadMem. No memory replacement happens and config file is empty.
If I comment MyBBox line or use older Chisel, replacement works.
Chisel that works:
val defaultVersions = Map(
"chisel3" -> "3.2.5",
"chisel-iotesters" -> "1.3.5"
)
This one fails (so far the latest one):
val defaultVersions = Map(
"chisel3" -> "3.4.2",
"chisel-iotesters" -> "1.5.2"
)
Scala code:
package explore
import chisel3._
import chisel3.util._
class MemoryInst extends Module {
val bitsDatNb = 64
val bitsAddrNb = 9
val io = IO(new Bundle {
val wAddr = Input(UInt(bitsAddrNb.W))
val wData = Input(UInt(bitsDatNb.W))
val wEn = Input(Bool())
val rAddr = Input(UInt(bitsAddrNb.W))
val rEn = Input(Bool())
val rData = Output(UInt(bitsDatNb.W))
})
val myBbox = Module( new MyBBox())
val memFile = SyncReadMem(1<<bitsAddrNb, UInt(bitsDatNb.W))
when(io.wEn) {
memFile.write(io.wAddr, io.wData)
}
io.rData := memFile.read(io.rAddr, io.rEn)
}
class MyBBox() extends BlackBox(
Map(
"LEN_BITS" -> 8,
"ADDR_BITS" -> 10,
"DATA_BITS" -> 64)) with HasBlackBoxResource {
val io = IO(new Bundle {
val clock = Input(Clock())
val reset = Input(Bool())
})
setResource("/verilog/someverilog.v")
}
object MemtestInst extends App {
chisel3.Driver.execute(args, () => new MemoryInst)
}
Am I missing something?
Thanks in advance!

Answer 1

I had the same problem with Chisel version 3.4.0
I can confirm that the code similar you have works with memory mapping without blackbox and not with it. I suggest the following adding
import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}
and changing
object MemtestInst extends App {
chisel3.Driver.execute(args, () => new MemoryInst)
}
to
object MemtestInst extends App {
val annos = Seq(ChiselGeneratorAnnotation(() =>
new MemoryInst()
))
(new ChiselStage).execute(args, annos)
}
I think chisel3.Driver.execute is with 3.4 and later.