firrtl_interpreter.InterpreterException: error: ConcreteSInt(303, 9) bad width 9 needs 10 - chisel

Question

I've got a module that generates the following FIRRTL
module Deep_1 :
input clock : Clock
input reset : UInt<1>
output io : {in : {flip data : SInt<8>[4]}, constIn : {flip data : SInt<8>[4]}, ...}
...
... (elided)
...
wire inputData : SInt<8>[4] #[Deep.scala 32:23]
wire constInputData : SInt<8>[4] #[Deep.scala 33:28]
reg outputData : SInt<8>[4], clock #[Deep.scala 34:23]
inputData[2] <= io.in.data[2] #[Deep.scala 37:18]
constInputData[2] <= io.constIn.data[2] #[Deep.scala 38:23]
node _T_209 = add(inputData[2], constInputData[2]) #[package.scala 32:44]
node _T_210 = tail(_T_209, 1) #[package.scala 32:44]
node _T_211 = asSInt(_T_210) #[package.scala 32:44]
outputData[2] <= _T_211 #[Deep.scala 39:19]
...
... (elided)
...
but when I try to run my tests through the firrtl interpreter I get
Exception during evaluation: error: ConcreteSInt(303, 9) bad width 9 needs 10 #[package.scala 32:44:#82.4]
Expression Evaluation stack
0 dut.outputData_2:Reg -> dut._T_211
1 dut._T_211:Node -> asSInt(dut._T_210)
2 dut._T_210:Node -> tail(dut._T_209, 1)
3 dut._T_209:Node -> add(dut.inputData_2, dut.constInputData_2)
If I understand this correctly, it is saying that the width of outputData[2] is 9 but 10 is needed. However, from what I can see, the width of both outputData[2] and _T_211 should be 8, the first by definition and the second as a result of the add() and tail() operations applied.
What am I missing?

Answer 1

How current is your software? I cannot reproduce the problem with current versions of the interpreter. I used the following firrtl test in the gist Attempt to reproduce firrtl-interpreter width error where I un-elided. As #Kamyar said, can you try using the Treadle backend. It is more modern and better supported at this point than is the interpreter.