How do you implement active-low reset with named ports? - chisel

Question

I'm attempting to use Records along with 'withClockAndReset()' to create an interface Vivado will use, along with the expected negated reset.
The approach so far looks like:
// Borrowed from https://github.com/freechipsproject/chisel3/blob/master/src/test/scala/chiselTests/RecordSpec.scala
final class CustomBundle(elts: (String, Data)*) extends Record {
val elements = ListMap(elts map { case (field, elt) =>
requireIsChiselType(elt)
field -> elt
}: _*)
def apply(elt: String): Data = elements(elt)
override def cloneType: this.type = {
val cloned = elts.map { case (n, d) => n -> DataMirror.internal.chiselTypeClone(d) }
(new CustomBundle(cloned: _*)).asInstanceOf[this.type]
}
}
class vivadoSlaveWrapper(regCount:Int, addrBits: Int, dataBits:Int) extends RawModule {
val io = IO(new CustomBundle(
"aclk" -> Input(Clock()),
"aresetn" -> Input(Bool()),
"s_axi_awaddr" -> Input(UInt(addrBits.W)),
"s_axi_awvalid" -> Input(Bool()),
"s_axi_awready" -> Output(Bool()),
"s_axi_awprot" -> Input(UInt(3.W)),
"s_axi_bresp" -> Output(UInt(2.W)),
"s_axi_bvalid" -> Output(Bool()),
"s_axi_bready" -> Input(Bool()),
"s_axi_wdata" -> Input(UInt(dataBits.W)),
"s_axi_wvalid" -> Input(Bool()),
"s_axi_wready" -> Output(Bool()),
"s_axi_wstrb" -> Input(UInt({dataBits/8}.W)),
"s_axi_araddr" -> Input(UInt(addrBits.W)),
"s_axi_arvalid" -> Input(Bool()),
"s_axi_arready" -> Output(Bool()),
"s_axi_arprot" -> Input(UInt(3.W)),
"s_axi_rdata" -> Output(UInt(dataBits.W)),
"s_axi_rvalid" -> Output(Bool()),
"s_axi_rready" -> Input(Bool()),
"s_axi_rresp" -> Output(UInt(2.W))
))
withClockAndReset(io("aclk"), ~io("aresetn")) {
val mod = Module( new simpleRegBank(regCount, addrBits, dataBits) )
mod.io.aw.addr := io("s_axi_awaddr" )
mod.io.aw.valid := io("s_axi_awvalid")
io("s_axi_awready") := mod.io.aw.ready
mod.io.aw.prot := io("s_axi_awprot" )
io("s_axi_bresp" ) := mod.io.b.bits
io("s_axi_bvalid" ) := mod.io.b.valid
mod.io.b.ready := io("s_axi_bready" )
mod.io.w.data := io("s_axi_wdata" )
mod.io.w.valid := io("s_axi_wvalid" )
io("s_axi_wready" ) := mod.io.w.ready
mod.io.w.strb := io("s_axi_wstrb" )
mod.io.ar.addr :=io("s_axi_araddr" )
mod.io.ar.valid := io("s_axi_arvalid")
io("s_axi_arready") := mod.io.ar.ready
mod.io.ar.prot := io("s_axi_arprot" )
io("s_axi_rdata" ) := mod.io.r.data
io("s_axi_rvalid" ) := mod.io.r.valid
mod.io.r.ready := io("s_axi_rready" )
io("s_axi_rresp" ) := mod.io.r.resp
}
}
but this results in errors around which types are being used in this case. I suspect this is mostly a Scala question, but I'm not quite sure how to resolve this to work for Clock and Reset.
The error is as below:
[error] /.../chisel/src/main/scala/axi4lite/axi4lite.scala:219:23: type mismatch;
[error] found : chisel3.Data
[error] (which expands to) chisel3.core.Data
[error] required: chisel3.core.Clock
[error] withClockAndReset(io("aclk"), io("aresetn")) {
[error] ^
[error] /.../chisel/src/main/scala/axi4lite/axi4lite.scala:219:35: type mismatch;
[error] found : chisel3.Data
[error] (which expands to) chisel3.core.Data
[error] required: chisel3.core.Reset
[error] withClockAndReset(io("aclk"), io("aresetn")) {
[error] ^
[error] two errors found
[error] (Compile / compileIncremental) Compilation failed