How do you instanciate a same module twice? - chisel

Question

I am developping a code in chisel, and tried to instanciate a module Encryption twice.
If I just use Enc0 in the code below, it works fine.
But if I use Enc0 and Enc1, then I have the following error appearing for line 40 :
[error] chisel3.internal.ChiselException: Connection between sink (chisel3.core.UInt#1fc1) and source (chisel3.core.UInt#1f8d) failed #: Sink or source unavailable to current module.
30 val Enc0 = Module(new Encryption())
31 Enc0.io.lab1 := a0
32 Enc0.io.lab2 := b0
33 Enc0.io.lab3 := a0 & b0
34 Enc0.io.key := io.secret_key
35 Enc0.io.wire_id := io.wire_index
36 Enc0.io.go := io.go
37 val tab0 = Enc0.io.enc
38 io.garbled_table.out0 := tab0
39
40 val Enc1 = Module(new Encryption())
41 Enc1.io.lab1 := a0
42 Enc1.io.lab2 := b1
43 Enc1.io.lab3 := a0 & b1
44 Enc1.io.key := io.secret_key
45 Enc1.io.wire_id := io.wire_index
46 Enc1.io.go := io.go
47 val tab1 = Enc1.io.enc
48 io.garbled_table.out1 := tab1
All the inputs and outputs of Enc0 and Enc1 are correctly connected, since Enc0 can work when I comment all lines 40-48.
So I don't know why it is not working

Answer 1

I have expanded this out to a module that does compile. Perhaps you can compare this to your example above. It is probably an error in the IO direction of one of your intermediate wires. It's less than ideal (there is working being done to improve error messages like this) but can you figure out which line is the problem by uncommenting replacing the right hand sides of 40-48 with DontCare, and replacing those one by one until you narrow down the offending line.
My example that seems to build.
import chisel3._
import chisel3.experimental.MultiIOModule
class Encryption extends Module {
val io = IO(new Bundle {
val lab1 = Input(Bool())
val lab2 = Input(Bool())
val lab3 = Input(Bool())
val key = Input(UInt(8.W))
val wire_id = Input(UInt(8.W))
val go = Input(UInt(8.W))
val enc = Output(UInt(8.W))
})
}
class Parent extends MultiIOModule {
val a0 = IO(Input(Bool()))
val b0 = IO(Input(Bool()))
val a1 = IO(Input(Bool()))
val b1 = IO(Input(Bool()))
val secret_key = IO(Input(UInt(8.W)))
val io = IO(new Bundle {
val secret_key = Input(UInt(8.W))
val wire_index = Input(UInt(8.W))
val garbled_table = new Bundle {
val out0 = Output(UInt(8.W))
val out1 = Output(UInt(8.W))
}
val go = Input(UInt(8.W))
})
val Enc0 = Module(new Encryption())
Enc0.io.lab1 := a0
Enc0.io.lab2 := b0
Enc0.io.lab3 := a0 & b0
Enc0.io.key := io.secret_key
Enc0.io.wire_id := io.wire_index
Enc0.io.go := io.go
val tab0 = Enc0.io.enc
io.garbled_table.out0 := tab0
val Enc1 = Module(new Encryption())
Enc1.io.lab1 := a0
Enc1.io.lab2 := b1
Enc1.io.lab3 := a0 & b1
Enc1.io.key := io.secret_key
Enc1.io.wire_id := io.wire_index
Enc1.io.go := io.go
val tab1 = Enc1.io.enc
io.garbled_table.out1 := tab1
}
object Encryption {
def main(args: Array[String]): Unit = {
println(Driver.emit(() => new Parent))
}
}