What is the meaning of :*= and :=* operators? - chisel

I see some examples in the RocketChip, but could not find info in the API reference
masterNode :=* tlOtherMastersNode
DisableMonitors { implicit p => tlSlaveXbar.node :*= slaveNode }

These are not Chisel operators. Instead, they're defined and used by Rocket Chip's diplomacy package. These are shorthand operators for doing different types of binding between diplomatic nodes.
No published API documentation for this exists, but you can start poking around in the diplomacy package. The releveant location where these are defined is src/main/scala/diplomacy/Nodes.scala.

The pull request comment on this API is very infomative.
Commonly, A := B creates a pair of master and slave ports in A and B.
A :=* B means the number of port pairs is decided by number of B := Other,
and A :*= B vice versa.
The most counterintuitive part is that the duplication of links is not achieved by
duplication of the intermediate module, but the intermediate module's expanding of port list.
I have written a simple example to explore star connectors' behavior.
In the following code snippet, an TLIdentifyNode connects 3 TLClientNode using :=,
and then it connects to a crossbar node using :=* as master to crossbar.
Meanwhile, an TLIdentifyNode connects 2 TLManagerNode using :=,
and then it connects to the same crossbar node using :*= as salve to crossbar.
import chisel3._
import chisel3.core.dontTouch
import freechips.rocketchip.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
class ClientConnector(implicit p: Parameters) extends LazyModule {
val node = TLIdentityNode()
override lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((bundleIn, edgeIn), (bundleOut, edgeOut)) =>
bundleOut <> bundleIn
}
}
}
class ManagerConnector(implicit p: Parameters) extends LazyModule {
val node = TLIdentityNode()
override lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((bundleIn, edgeIn), (bundleOut, edgeOut)) =>
bundleOut <> bundleIn
}
}
}
class Client(implicit p: Parameters) extends LazyModule {
val node = TLClientNode(
portParams = Seq(
TLClientPortParameters(Seq(
TLClientParameters("myclient1", IdRange(0, 1), supportsGet = TransferSizes(4), supportsProbe = TransferSizes(4))
))
)
)
override lazy val module = new LazyModuleImp(this) {
node.out.foreach { case(bundle, edge) =>
val (legal, a) = edge.Get(0.U, 0x1000.U, 2.U)
bundle.a.bits := a
bundle.a.valid := legal
bundle.d.ready := true.B
dontTouch(bundle)
}
}
}
class Manager(base: Int)(implicit p: Parameters) extends LazyModule {
val node = TLManagerNode(Seq(TLManagerPortParameters(Seq(TLManagerParameters(
address = Seq(AddressSet(base, 0xffff)),
supportsGet = TransferSizes(4)
)), beatBytes = 4)))
override lazy val module = new LazyModuleImp(this) {
node.in.foreach { case (bundle, edge) =>
when (bundle.a.fire()) {
val d = edge.AccessAck(bundle.a.bits, 0xdeadbeafL.U)
bundle.d.bits := d
bundle.d.valid := true.B
}
bundle.a.ready := true.B
}
}
}
class Playground(implicit p: Parameters) extends LazyModule {
val xbr = TLXbar()
val clientConnectors = LazyModule(new ClientConnector())
val managerConnectors = LazyModule(new ManagerConnector())
val clients = Seq.fill(3) { LazyModule(new Client()).node }
val managers = Seq.tabulate(2) { i: Int => LazyModule(new Manager(0x10000 * i)).node }
clients.foreach(clientConnectors.node := _)
managers.foreach(_ := managerConnectors.node)
managerConnectors.node :*= xbr
xbr :=* clientConnectors.node
override lazy val module = new LazyModuleImp(this) {
}
}
The corresponding verilog code of ManagerConnector is (in brief):
module ManagerConnector(
`tilelink_bundle(auto_in_0),
`tilelink_bundle(auto_in_1),
`tilelink_bundle(auto_out_0),
`tilelink_bundle(auto_out_1)
);
// ...
endmodule
We can see diplomacy framework is only responsible for parameter negotiation, port list generation and port connection. The duplication introduced by * connection is guaranteed by the common code pattern:
(node.in zip node.out) foreach { ... }
In my opinion, this API simplifies connection between crossbar node and various nodes inside a specific module, and keeps the connection syntax consistent.
[Reference] A rocketchip reading note: https://github.com/cnrv/rocket-chip-read/blob/master/diplomacy/Nodes.md

It might be useful to read the documentation on diplomacy by lowrisc: https://www.lowrisc.org/docs/diplomacy/

Related

Generate dynamic bundle

In my project, I have many different custom Bundle.
They can be completely different.
For example these ones:
class MyBundle extends Bundle {
val v1 = UInt(8.W)
val v2 = Bool()
val v3 = UInt(4.W)
}
class MyBundle2 extends Bundle {
val v4 = UInt(18.W)
val v5 = UInt(2.W)
}
...
Instead of manually creating new Bundle to perform each operation, I want to be able to generate for all of them the corresponding Bundle.
So for MyBundle, I want to do:
// Must be generated for each Bundle
class MyGenBundle extends Bundle {
val v1 = UInt(log2Ceil(8 + 1).W) // width = MyBundle.v1 width + 1
val v2 = UInt(log2Ceil(1 + 1).W) // width = MyBundle.v2 width + 1
val v3 = UInt(log2Ceil(4 + 1).W) // width = MyBundle.v3 width + 1
}
class MyModule extends Module {
...
...
val w_b = Wire(new MyBundle())
val w_gb = Wire(new MyGenBundle())
// Must be automated for each Bundle
w_gb.v1 := PopCount(w_b.v1)
w_gb.v2 := PopCount(w_b.v2)
w_gb.v3 := PopCount(w_b.v3)
}
My goal is to automatically generate MyGenBundle (or similar directly in MyModule) from MyBundle, and perform in MyModule the same operation to all signals.
It also means that I need to dynamically address all signals in each Bundle.
Finally, I think the solution can have the following form:
val w_b = Wire(new MyBundle())
val w_gb = Wire(new AutoGenBundle(new MyBundle())) // AutoGenBundle generates a Bundle from parameter
val v_sig = Seq(v1, v1, v3) // Can be recovered automatically
// from w_b.elements I think
foreach (s <- v_sig) {
w_gb."s" := PopCount(w_b."s") // Here "s" the dynamic name of the signal
} // But how in the real case ?
Is this working technically possible in Chisel/Scala?
If so, do you have any ideas for implementing it?
Basic solution is to use the MixedVec chisel type for GenericBundle
class MyBundle extends Bundle {
val v1 = UInt(8.W)
val v2 = Bool()
val v3 = UInt(4.W)
}
class GenericBundle[T <: Bundle](data: T) extends Bundle {
val v = MixedVec(data.elements.values.map(x => UInt(log2Ceil(x.getWidth + 1).W)).toList)
def popCount(data: T): Unit = {
data.elements.values.zip(v).foreach { case (left, right) =>
right := PopCount(left.asUInt())
}
}
}
class MyModule extends MultiIOModule {
val w_b = IO(Input(new MyBundle))
val w_gb = IO(Output(new GenericBundle(w_b)))
w_gb.popCount(w_b)
}

test rocket chip util 'Arbiters.scala', got error 'bits operated ... must be hardware ..."

I copied a rocket-chip util module 'Arbiters.scala' to a separate work directory, test with the following code:
object try_arbiter extends App {
chisel3.Driver.execute(args, () => new HellaCountingArbiter(UInt(4.W), 3, 5))
}
There's no problem when compiling. However, in the step 'Elaborating design...', it reported [error] chisel3.core.Binding$ExpectedHardwareException: mux condition 'chisel3.core.Bool#46' must be hardware, not a bare Chisel type"
The related code is
PriorityEncoder(io.in.map(_.valid))
when I change this line to the following one, the error's gone (the scala code still has this kind of errs, but not in this line).
PriorityEncoder(io.in.map(x => Wire(x.valid)))
The rocket chip codes should have been evaluated for many times, right? I think there must have sth I have missed... Some configurations?
Thank you for any hints!
Appendix(the Arbiters.scala):
package rocket_examples
import chisel3._
import chisel3.util._
/** A generalized locking RR arbiter that addresses the limitations of the
* version in the Chisel standard library */
abstract class HellaLockingArbiter[T <: Data](typ: T, arbN: Int, rr: Boolean = false)
extends Module {
val io = new Bundle {
val in = Vec(arbN, Decoupled(typ.cloneType)).flip
val out = Decoupled(typ.cloneType)
}
def rotateLeft[T <: Data](norm: Vec[T], rot: UInt): Vec[T] = {
val n = norm.size
Vec.tabulate(n) { i =>
Mux(rot < UInt(n - i), norm(UInt(i) + rot), norm(rot - UInt(n - i)))
}
}
val lockIdx = Reg(init = UInt(0, log2Up(arbN)))
val locked = Reg(init = Bool(false))
val choice = if (rr) {
PriorityMux(
rotateLeft(Vec(io.in.map(_.valid)), lockIdx + UInt(1)),
rotateLeft(Vec((0 until arbN).map(UInt(_))), lockIdx + UInt(1)))
} else {
PriorityEncoder(io.in.map(_.valid))
}
val chosen = Mux(locked, lockIdx, choice)
for (i <- 0 until arbN) {
io.in(i).ready := io.out.ready && chosen === UInt(i)
}
io.out.valid := io.in(chosen).valid
io.out.bits := io.in(chosen).bits
}
/** This locking arbiter determines when it is safe to unlock
* by peeking at the data */
class HellaPeekingArbiter[T <: Data](
typ: T, arbN: Int,
canUnlock: T => Bool,
needsLock: Option[T => Bool] = None,
rr: Boolean = false)
extends HellaLockingArbiter(typ, arbN, rr) {
def realNeedsLock(data: T): Bool =
needsLock.map(_(data)).getOrElse(Bool(true))
when (io.out.fire()) {
when (!locked && realNeedsLock(io.out.bits)) {
lockIdx := choice
locked := Bool(true)
}
// the unlock statement takes precedent
when (canUnlock(io.out.bits)) {
locked := Bool(false)
}
}
}
/** This arbiter determines when it is safe to unlock by counting transactions */
class HellaCountingArbiter[T <: Data](
typ: T, arbN: Int, count: Int,
val needsLock: Option[T => Bool] = None,
rr: Boolean = false)
extends HellaLockingArbiter(typ, arbN, rr) {
def realNeedsLock(data: T): Bool =
needsLock.map(_(data)).getOrElse(Bool(true))
// if count is 1, you should use a non-locking arbiter
require(count > 1, "CountingArbiter cannot have count <= 1")
val lock_ctr = Counter(count)
when (io.out.fire()) {
when (!locked && realNeedsLock(io.out.bits)) {
lockIdx := choice
locked := Bool(true)
lock_ctr.inc()
}
when (locked) {
when (lock_ctr.inc()) { locked := Bool(false) }
}
}
}
The issue is that almost all of the code in rocket-chip has been written against older Chisel2-style APIs and should be compiled with the compatibility wrapper import Chisel._. I see you used import chisel3._ which has somewhat stricter semantics.
For this specific case, the difference between Chisel2 and Chisel3 is that ports (val io) must be wrapped in IO(...), ie.
val io = IO(new Bundle {
val in = Flipped(Vec(arbN, Decoupled(typ)))
val out = Decoupled(typ)
})
Note that I also changed Vec(arbN, Decoupled(typ.cloneType)).flip to Flipped(Vec(arbN, Decoupled(typ))) and removed the .cloneType on val out. The latter two changes are not required for this to compile but they will be flagged as deprecation warnings as of Chisel 3.1.2.

Type mismatch: expected :: [String, HNil] => op_rabbit.Handler, actual: String => op_rabbit.Handler

I took the following code from here in order to consume messages from RabbitMQ. Once a new message is consumed, I want to execute val init = new Initiator() in order to run some calculations on this message.
In the original code the messages are parsed as follows:
package io.ticofab.scalarabbitmqexample.model
import play.api.libs.json.Json
/**
* This is the kind of object that our listener expects in Json format from the queue. So like
* {
* "name" : "xxxx",
* "version" : 1234
* }
*
* #param name An arbitrary String
* #param version An arbitrary Int
*/
case class MyObject(name: String, version: Int)
object MyObject {
implicit def myObjectFormat = Json.format[MyObject]
}
In my case the parsing is complicated and I don't want to parse the Json String in MyObject. What I want is to run body(as[String]) instead of body(as[MyObject]) { (see the code below). Then I'll do parsing inside init.run(obj) using import spray.json._.
So, my goal is to convert obj into String. But if I do so, I get the following compilation error:
Type mismatch: expected :: [String, HNil] => op_rabbit.Handler,
actual: String => op_rabbit.Handler.
package org.test.akka_actors
import akka.actor.{Actor, ActorLogging, Props}
import com.spingo.op_rabbit.Directives._
import com.spingo.op_rabbit.{RabbitControl, Subscription, SubscriptionRef}
import com.typesafe.config.ConfigFactory
import org.test.Initiator
import org.test.akka_actors.QueueListener.{Listen, Terminate}
import org.test.query.QueryObject
import scala.concurrent.ExecutionContext.Implicits.global
object QueueListener {
case object Listen
case object Terminate
def props = Props(new QueueListener)
}
class QueueListener extends Actor with ActorLogging {
// read info from configuration
val conf = ConfigFactory.load()
val QUEUE = conf.getString("op-rabbit.rabbit-queue")
// instantiate a rabbit mq controller
val RABBIT_CONTROL = context.actorOf(Props[RabbitControl])
// references to the queue subscriptions
var queueSubscription: Option[SubscriptionRef] = None
override def receive: Receive = {
case Listen =>
// initialize a queue subscription
queueSubscription = Some(
Subscription.run(RABBIT_CONTROL) {
channel(qos = 3) {
consume(queue(QUEUE)) {
body(as[String]) {
(obj) =>
log.debug(s"received the query $obj")
val init = new Initiator()
init.run(obj)
ack
}
}
}
}
)
case Terminate =>
// close the subscription
queueSubscription.foreach(_.close())
}
}

Using ScalaCheck with PeekPokeTester

Here is chisel3 test that uses ScalaCheck to perform property checking on a simple combinational circuit.
package stackoverflow
import org.scalatest.{ Matchers, FlatSpec, GivenWhenThen}
import org.scalacheck.{ Properties, Gen, Arbitrary}
import org.scalacheck.Prop.{ forAll, AnyOperators, collect}
import chisel3._
import firrtl_interpreter.InterpretiveTester
object G {
val width = 8
}
class Add extends Module {
val io = IO(new Bundle {
val a = Input(UInt(G.width.W))
val b = Input(UInt(G.width.W))
val o = Output(UInt(G.width.W))
})
io.o := io.a + io.b
}
class AddTester {
val s = chisel3.Driver.emit( () => new Add)
val tester = new InterpretiveTester( s)
def run( a : Int, b : Int) = {
val result = (a + b) & ((1 << G.width)-1)
tester.poke( s"io_a", a)
tester.poke( s"io_b", b)
tester.peek( s"io_o") ?= result
}
}
object AddTest extends Properties("Add") {
val t = new AddTester
val gen = Gen.choose(0,(1 << G.width)-1)
property("Add") = forAll( gen, gen) {
case (a:Int,b:Int) => t.run( a, b)
}
}
This uses the firrtl interpreter directly. Does anyone know how to do something similar using the PeekPokeTester so I can use the verilator and vcs backends as well?
Is this close to what you have in mind? It's a lot more scalatesty in form. I haven't been able to get the gen stuff working here (there is some kind of weird interaction with chisel), and I'm more familiar with FreeSpec so I started with it. I also threw a printf and a println in so you could believe it was working. This works with the interpreter backend as well.
import org.scalatest.FreeSpec
import org.scalacheck.Prop.AnyOperators
import chisel3._
import chisel3.iotesters.PeekPokeTester
class Add2 extends Module {
val io = IO(new Bundle {
val a = Input(UInt(G.width.W))
val b = Input(UInt(G.width.W))
val o = Output(UInt(G.width.W))
})
io.o := io.a + io.b
printf("%d = %d + %d\n", io.o, io.a, io.b)
}
class ScalaTestyTester extends FreeSpec {
"scalatest verilator test" in {
iotesters.Driver.execute(Array("--backend-name", "verilator"), () => new Add2) { c =>
new PeekPokeTester(c) {
for(_ <- 0 until 10) {
val a = BigInt(G.width, scala.util.Random)
val b = BigInt(G.width, scala.util.Random)
println(s"testing a = $a b = $b")
val result = (a + b) & ((1 << G.width) - 1)
poke(c.io.a, a)
poke(c.io.b, b)
step(1)
peek(c.io.o) ?= result
}
}
}
}
}

Conditional port in a Chisel Module

I have a selectable feature which is not normally required. However to support this feature, some I/O ports should be added to the origin Module I/O port.
I am doing it in this way:
import Chisel._
class TestModule extends Module {
class IOBundle extends Bundle {
val i = Bool(INPUT)
val o = Bool(OUTPUT)
}
class IOBundle_EXT extends IOBundle {
val o_ext = Bool(OUTPUT)
}
val io = if(true) new IOBundle_EXT else new IOBundle;
io.o := io.i
io.o_ext := io.i
}
After running sbt "run TestModule --backend c --compile --test --genHarness", the compiler complains:
[error] xxxx/test/condi_port.scala:17: value o_ext is not a member of TestModule.this.IOBundle
[error] io.o_ext := io.i
[error] ^
[error] one error found
[error] (compile:compile) Compilation failed
So the if statement has no effect. val io is still assigned to IOBundle, rather than the extended IOBoundle_EXT, which makes no sense to me.
Chisel now supports Options in IO bundles.
As an example, I explored Options here (https://github.com/ucb-bar/riscv-boom/commit/da6edcb4b7bec341e31a55567ee04c8a1431d659), but here's a summary:
class MyBundle extends Bundle
{
val my_ext = if (SOME_SWITCH) Some(ExtBundle) else None
}
...
io.my_ext match
{
case Some(b: ExtBundle) =>
my_ext.a := Bool(false)
...
case _ => require (!SOME_SWITCH)
}
It's incredibly verbose, but I was able to get it working even when doing bulk connects and hiding bundles within bundles, etc.
Even though the compiler could determine that only one result is possible (the expression is always true), the type system sets the type of the result equal to the greatest common subtype of the two possible (true or false) sub-expressions.
You can verify this trivially with the following:
scala> val result = if (true) 1 else "one"
result: Any = 1
Try this:
import Chisel._
class TestModule(val useEXT : Boolean) extends Module {
class IOBundle extends Bundle {
val i = Bool(INPUT)
val o = Bool(OUTPUT)
}
class IOBundle_EXT extends IOBundle {
val o_ext = Bool(OUTPUT)
}
val io = {
if(useEXT) {
val res = new IOBundle_EXT; res.o_ext := res.i; res
} else {
new IOBundle }};
io.o := io.i
}