Uppaal template parameters - function

I am using UPPAAL 4.1.19 and I am following the train tutorial, given in this. In Train template, I put the parameters int[0,N] e, const int id and in the system declaration I declare Train1=Train(el, 1); and the system returns me "Incompatible argument" error for e1. I don't understand why it is actually incompatible? I have declared N as a constant equal to 5 in the global declarations, as well as el, but still it doesn't seem to work. Any idea?

Try int[0,N] &e, const int id, similarly as here (page 6): https://www.it.uu.se/research/group/darts/uppaal/small_tutorial.pdf.

Related

Indexing of elements in a Seq of string with chisel

I have, tab=Array(1.U, 6.U, 5.U, 2.U, 4.U, 3.U) and Y=Seq(b,g,g,g,b,g), tab is an array of UInt.
I want to do a map on tab as follows:
tab.map(case idx=>Y(idx))
But I keep getting the error: found chisel3.core.UInt, required Int.
I tried using the function peek() to convert idx to an Int by doing
tab.map(case idx=>Y(peek(idx).toInt)
but I get peek not found. I also saw that I cannot convert a chisel UInt to an Int here but did not understand the use of peek well with the example given. So please, is there another approach to do the above?
Thanks!
The immediate problem is that you cannot access the elements of scala collections using a hardware construct like UInt or SInt. It should work if you wrap Y in a Vec. Depending on your overall module this would probably look like
val YVec = VecInit(Y)
val mappedY = tab.map { case idx => YVec(idx) }

Result of a function with parameters passed by name

Consider the following pseudocode snippet:
int c = 2;
int bar(int a)
{
c = c + 2;
return a * 2;
}
int foo(void)
{
return(bar(c + 1));
}
I'm asked to determine what the return value of foo(); will be, assuming that the language used passes all parameters by name.
My reasoning is that, since parameters are passed by name, c+1 won't be evaluated when bar(c+1) is called, but only when the first instance of the formal parameter a is encountered in bar, that is in the return a*2 line, after bar has modified the global variable c, so, since c+1 has to be evaluated in the caller's environment, that is in foo's environment and foo has only the global c in its scope it will be evaluated as 4+1, giving a fine return value of 10.
My doubt is whether this should be 6 instead, if I blindly apply a syntactical substitution rule, as passing by name requires the fifth line should be interpreted as return c+1*2, instead of return (c+1)*2, so what is the correct approach here?
For reference I'm using the definition of passing by name provided in section 7.1.2 of Programming Languages:Principles and Paradgigms by Gabbrielli and Martini

How to add parameters into an [ MQL4 ] function through an Array?

I want to build a function for some code that I use often in my MQL4 programming that outputs to a file data resulting from optimisation runs.
I already have the working code but I am having a difficulty with passing parameters.
Some of the function parameters, that I need to access inside the function and so these need to be passed as parameters, are global, user defined variables - eg as: input int Moving_Average_period = .... ;.
The next time I use the function, this variable may not be required but another(s) will
This variable reference needs to appear in a FileWrite() statement eg:
FileWrite( h, Counter, Moving_Average_period, StopLoss, .......... );
any ideas please - thanks in advance.
Declare the function with an Array(s) in the call-signature:
Simply put,
void aFunctionWithValuesInARRAYs( int const anArrayOfINTs[],
double const anArrayOfDOUBLEs[],
datetime const anArrayOfDATETIMEs[]
) {
// ------------------------ ^
// PROCESS DATA AS YOU NEED +-- pre-loading and updating values
// ------------------------ in each anArrayOf*s[] is a very
// Q.E.D. flexible external-responsibility
...
}

Why isn't parameter being passed properly in Verilog?

I have two verlog modules as seen below. The parameter statement is supposed too allow me to pass the bus width i'd like to instantiate another module at.
I keep getting an error when trying to compile saying "Port expression 64 does not match expected width 1 or 2."
module LabL3;
parameter SIZE = 64;
reg [SIZE-1:0]a;
reg [SIZE-1:0]b;
reg c;
wire [SIZE-1:0]z;
integer i,j,k;
yMux #(SIZE) mux(z,a,b,c);
initial
begin
for(i=0;i<4;i=i+1)begin
for(j=0;j<4;j=j+1)begin
for(k=0;k<2;k=k+1)begin
a=i;b=j;c=k;
#1$display("a=%d b=%d c=%d z=%d",a,b,c,z);
end
end
end
end
endmodule
and the other file is:
module yMux(z,a,b,c);
parameter SIZE= 0;
output [SIZE-1:0]z;
input [SIZE-1:0]a,b;
input c;
yMux1 mux[SIZE-1:0](z,a,b,c);
endmodule
and lastly
module yMux1(z,a,b,c);
output z;
input a,b,c;
wire not_C, upper, lower;
not my_not(notC,c);
and upperAnd(upper,a,notC);
and lowerAnd(lower,c,b);
or my_or(z,upper,lower);
endmodule
and the command I am using is: iverilog LabL3.v yMux1.v yMux.v
I have tried the different syntax's for parameter passing. All give the same result.
Any hints would greatly be appreciated.
- Chris
You are using vectored instances:
yMux1 mux[SIZE-1:0](z,a,b,c);
Where you end up with SIZE number of yMux1 instances. This should connect z,a,b bitwise correctly and connect the single bit c to all yMux1 c ports via replication.
If you really want to drive all c ports to the same value I would try manually replicating the port with:
yMux1 mux[SIZE-1:0](z,a,b,{SIZE{c}});
Example on EDAPlayground looks fine to me. Could be an issue with the specific tool not supporting vectored instances correctly.
When possible I would recommend using named port connections (ANSI header style) from section 23.2.1 of the SystemVerilog IEEE 1800-2012 Standard.
This style is very clear as to your design intent, I find it much easier to read which relates to less bugs. It also allows easier refactoring of the code due to the named connections and not being order dependent.
module LabL3;
parameter SIZE = 64;
reg [SIZE-1:0] a;
reg [SIZE-1:0] b;
reg c;
wire [SIZE-1:0] z;
yMux #(
.SIZE(SIZE)
) mux (
.z(z),
.a(a),
.b(b),
.c(c)
);
yMux definiton:
module yMux #(
parameter SIZE= 0
) (
output [SIZE-1:0] z,
input [SIZE-1:0] a,
input [SIZE-1:0] b,
input c
);
// ...
endmodule
An example of the above code on EDAPlayground.

Passing expression as a parameter in Call by reference

All,
When we are passing an expression as a parameter, how does the evaluation occur? Here is a small example. This is just a pseudocode kind of example:
f (x,y)
{
y = y+1;
x = x+y;
}
main()
{
a = 2; b = 2;
f(a+b, a)
print a;
}
When accessing variable x in f, does it access the address of the temp variable which contains the result of a+b or will it access the individual addresses of a and b and then evaluate the value of a+b
Please help.
Regards,
darkie15
Somewhat language dependent, but in C++
f(a+b, a)
evaluates a + b and and pushes the result of evaluation onto the stack and then passes references to this value to f(). This will only work if the first parameter is of f() is s const reference, as temporary objects like the result of a + b can only be bound to const references.
In C or C++, as long as x and y are not pointers (in which case the expression is not useful anyway), they are both evaluated before the function call and the VALUE of the result is pushed on the stack. There are no references involved, at all.
All parameters in C and C++ are always passed by value. If a reference type (eg int*, int&) is passed to the function, the VALUE of the reference is passed. While the referenced object may be changed by accessing eg *x within the function, the value of the reference still cannot be changed, because C and C++ parameters are always always always passed by value only.
EDIT: an exception in C and C++ is the case in which some overloaded operator is defined like the following:
T* operator+ (L lhs, R rhs) {return new T(lhs, rhs);}
and x is an L, and y is an R. In this case, the value of the T* generated by the function is pushed on the stack as a parameter. Don't write code like that, it confuses other programmers =D.