I'm learning MIPS so I wrote a simple C program and generated MIPS assembly with gcc and inside it there is this part
lui $28,%hi(__gnu_local_gp)
addiu $28,$28,%lo(__gnu_local_gp)
I know that lui means load upper immediate but I don't know what %hi(__gnu_local_gp) and %lo(__gnu_local_gp) mean; addiu means add immediate unsigned.
Are lo and hi registers?
If so what does % mean?
The instructions load the address of the symbol __gnu_local_gp into register 28.
__gnu_local_gp is a memory location that is used to store the Global Pointer, and register 28 is typically used to hold the Global Pointer.
'%hi' and '%lo' are builtin functions of the GNU assembler, and have nothing to do with the hi and lo registers in the MIPS architecture.
Related
There are a multitude of different instructions in MIPS. I'm currently learning about data and instruction cache.
Instruction cache simply takes what it can so to say, depending on the block size it might utilize spatial locality and fetch multiple instructions. But for data cache I have a harder time understanding when it fetches things from main memory and when it doesn't.
For example, the instruction lw $t0, 0x4C($0) will fetch a word of data stored in address 0x4C and depending on data cache capacity, sets, block size and so forth it will temporarily store in in a block in the cache if for that adress the valid bit or tag doesn't exist there.
In my litterature, an addi instruction does not fetch from memory, why? The only times it seems to need to fetch data from memory is when using the lw instruction, why?
I also have a question regarding registers in MIPS. If we're simply doing the instructions over the registers, then there will be no access to any main memory, correct? It will not even go to the data cache, correct? Are the registers the highest level in the memory heirarchy?
The reason addi doesn't "fetch from memory" is that it's using an immediate operand, as in, the program counter has already fetched the value that's going to be loaded. (Technically it is fetching from memory, since all code resides in some form of memory, but when literature refers to "memory" typically it's referring to a range of memory outside the program counter. When MIPS uses something like lw to load from memory, the CPU has no idea what value the destination register will have until the load is finished.
Just to illustrate this concept further, the original MIPS I architecture (which was used by the PlayStation 1) actually wouldn't finish loading from memory before the next instruction was already being worked on!
lw $t0,0($a0) ;load from the address pointed to by $a0
addi $t0,$t0,5 ;the value in $t0 hasn't been updated yet so this won't have the desired result.
The easiest solution to this was to put a nop after every lw. Chances are the version of MIPS you're using doesn't have this problem, so don't worry about it.
I am currently reading Computer Organization and Design by John L. Henessy for Architecture course. As far as I understood that $sp points to the most recently allocated address in the stack and $fp points to the begining of the stack. Why exactly do we need $fp? And how does they behave if a procedure calls another procedure? For example when stack grows, the stack pointer decrements, but what are the changes in $fp?
$fp contains the value of $sp just before the current function was called, i.e. the beginning of the current stack frame (wikipedia). $fp is useful for x86 machines where PUSH and POP are commonly used, and is less useful for MIPS, where $sp is typically adjusted once on entry to a function and $sp relative addressing can be used.
I'd really need a hand or two with this Assembly Mips CPU Excercise.
I have to determine input and output from: ALU(s), Jump-related MUX and from the Register File.
PC is 0x01D0 and the instruction I have to simulate is: beq $3, $7, -120
Regarding the ALU(s) I've no problem on those, I've got issues on MUX and RG.
As you can see on the image on the second jump-related MUX I don't know what to write regarding jump address [31-0].
The other problem I've got is within the Register File, I don't know what to write as input.(Instruction should be: 0x1067FFE2)
I was wondering if there was an easy method/code to display the contents of the instruction memory in hex format onto the the console in a MIPS program?
How many stalls do I need to execute the following instructions properly. I am a little confused with what I did, so I am here to see experts answers.
lw $1,0($2);
beq $1,$2,Label;
Note that the check whether the branch will occur or not will be done in decoding stage. But the source register rs of beq which is $1 in this case will be updated after writeback stage of lw instruction. So do we need to forward new data from Memory in memory stage to Decoding stage of beq instruction.
Here is the data path diagram:
The value that is fetched from the memory, is written to the register file in the write-back stage of the pipeline. Writes to the register file happen in the first half of the clock cycle, while reads from the register file happen in the second half of the clock cycle.
The value that is written to the register file can thus be read in the same clock cycle as it is written to the register file. Thus forwarding is not effective here.
As for the number of stalls needed, you need to insert two bubbles into the pipeline, as the lw instruction should be in the write back stage when the beq instruction is in the decode stage.
I hope this answers your question.