VHDL - BCD to Binary input buffer - issues displaying the result - binary

Question

I am using Vivado 2014.2 to write VHDL code for a BCD to Binary input buffer that could be used for a calculator or a combo lock.
My method is simple. to do x*10 it is the same as x(2 + 8) = x*2 + x*8.
x*2 = 1 left shift (2^1 = 2)
x*8 = 3 left shifts (2^3 = 8)
The output buffer(tempC) is shifted and added before the input is added. This is done so that when starting from null so that the first digit entered doesn't come out multiplied by 10.
My code compiles and runs on an artix 7 fpga, but I am having issues making sure that the output buffer(tempC) is working correctly. It refuses to output any data, but I am not sure why.
I could be adding the values together wrong but I dont think its that. Maybe i'm casting to a wrong data type?
Any help is greatly appreciated.
-- Engineer: greatgamer34
--
-- Create Date: 01/25/2017 04:57:02 PM
-- Design Name:
-- Module Name: buff - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity buff is
Port ( Data : in STD_LOGIC_VECTOR (3 downto 0); ----4bit BCD value input
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR (15 downto 0);
aout : out STD_LOGIC_VECTOR (6 downto 0));-- 7 segment display output for current state.
end buff;
architecture Behavioral of buff is
type states is (state0, state1, state2, state3);
signal currentstate, nextstate: states;
signal tempA: STD_LOGIC_VECTOR (15 downto 0);---used to store 'Data' for addition.
signal tempB: STD_LOGIC_VECTOR (15 downto 0);---used for x2('Data').
signal tempC: STD_LOGIC_VECTOR (15 downto 0);---used as output register.
signal tempD: STD_LOGIC_VECTOR (15 downto 0);---used for sending data to LED's.
signal tempE: STD_LOGIC_VECTOR (15 downto 0);---used for x8('Data')
begin
Process(Reset,clock)
Begin
if(Reset = '1') then
tempC <= "0000000000000000"; --clear tempC
tempA <= "0000000000000000"; --clear tempA
currentstate <= state0; -------reset state to 0
elsif(clock'event and clock = '1') then
output <= (tempD);--dispaly the output of the buffer
currentstate<=nextstate; -- advance states
end if;
end process;
process(currentstate)
begin
case currentstate is
when state0 =>
tempA(3 downto 0) <= Data; -- load in 4 bit data intoi 16 bit register
tempD <= (tempA); --output the input data(used for debugging)
nextstate <= state1;
aout <= not "1111110"; -- output on the 7 seg the number 0
when state1 =>
tempB <= tempC(14 downto 0) & '0'; --left shift tempC(the output register) save to tempB; this is the x2 multiplication
tempD <= (tempA); -- output the input data(used for debugging)
nextstate <= state2;
aout <= not "0110000"; -- output on the 7 seg the number 1
when state2 =>
tempE <= tempC(12 downto 0) & "000"; --left shift tempC(the output register) three times save to tempE; this is the x8 multiplication
--tempC <=std_logic_vector( unsigned(tempE) + unsigned(tempD)); (TESTING)
tempC <=std_logic_vector( ('0' & unsigned(tempE(14 downto 0))) + ('0' & unsigned(tempD(14 downto 0)))); --add the first 15 bits of tempD and tempE(this is how we multiply by 10)
tempD <= (tempC); -- output the x10 output register
nextstate <= state3;
aout <= not "1101101" ; -- output on the 7 seg the number2
when state3 =>
-- tempC <= ('0' & tempC(14 downto 0)) + ('0' & tempA(14 downto 0)); (TESTING)
tempC <= std_logic_vector( ('0' & unsigned(tempC(14 downto 0))) + ('0' & unsigned(tempA(14 downto 0)))); --add the 'Data' to the x10 shifted number.
tempD <= (tempC);
nextstate <= state0;
aout <= not "1111001"; -- output on the 7 seg the number3
end case;
end process;
end behavioral;

Answer 1

Answer:
tempC is reset in the clocked process and then gets new values assigned in the combinatorial process.
It is not allowed to assign a signals a value in two different processes. Also the sensitivity list of the combinatorial process is missing signals.
Observations:
Use logical names for your signals tempX is very confusing. Also I cant imagine that your BCD circuit will be called BUFF ;)
Check the sensitivity list of your combinatoric process.
Google on how a state machine needs to be constructed
Simulation of your design in very important (especially for larger designs)
have a look at the different tutorials online eg Xilinx Vivado
2015.2 Simulation Tutorial
Happy debugging

Answer 2

Okay with help from some of the comments and answers I was able to get it to work. The following is the code used.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity buff is
Port ( Data : in STD_LOGIC_VECTOR (3 downto 0); ----4bit BCD value input
Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR (15 downto 0);
aout : out STD_LOGIC_VECTOR (6 downto 0));-- 7 segment display output for current state.
end buff;
architecture Behavioral of buff is
type states is (state0, state1, state2, state3, state4);
signal currentstate, nextstate: states;
signal tempA: STD_LOGIC_VECTOR (3 downto 0);---used to store 'Data' for addition.
signal tempB: STD_LOGIC_VECTOR (15 downto 0);---used for x2('Data').
signal tempC: STD_LOGIC_VECTOR (15 downto 0);---used as output register.
signal tempD: STD_LOGIC_VECTOR (15 downto 0);---used for sending data to LED's.
signal tempE: STD_LOGIC_VECTOR (15 downto 0);---used for x8('Data')
signal tempF: STD_LOGIC_VECTOR (15 downto 0);
begin
Process(Reset,clock)
Begin
if(Reset = '1') then
currentstate <= state4;
Output <= "0000000000000000"; -------reset state
elsif(clock'event and clock = '1') then
Output <= tempD ;--display the output of the buffer
currentstate <= nextstate; -- advance states
end if;
end process;
process(currentstate)
begin
case currentstate is
when state0 =>
tempA <= Data; -- load in 4 bit data intoi 16 bit register
tempD(3 downto 0) <= tempA; --output the input data(used for debugging)
nextstate <= state1;
aout <= not "1111110"; -- output on the 7 seg the number 0
when state1 =>
tempB <= (tempC(14 downto 0) & "0"); --left shift tempC(the output register) save to tempB; this is the x2 multiplication
tempD <= (tempB); -- output the input data(used for debugging)
nextstate <= state2;
aout <= not "0110000"; -- output on the 7 seg the number 1
when state2 =>
tempE <= tempC(12 downto 0) & "000"; --left shift tempC(the output register) three times save to tempE; this is the x8 multiplication
--tempF <=std_logic_vector( unsigned(tempE) + unsigned(tempB)); --(TESTING)
tempF <=std_logic_vector( ('0' & unsigned(tempE(14 downto 0))) + ('0' & unsigned(tempB(14 downto 0)))); --add the first 15 bits of tempD and tempE(this is how we multiply by 10)
tempD <= tempE; -- output the x10 output register
nextstate <= state3;
aout <= not "1101101" ; -- output on the 7 seg the number2
when state3 =>
--tempC <=std_logic_vector( unsigned(tempC) + unsigned(tempA));
tempC <= std_logic_vector( ('0' & unsigned(tempF(14 downto 0))) + ("000000000000" & unsigned(tempA))); --add the 'Data' to the x10 shifted number.
tempD <= tempC;
nextstate <= state0;
aout <= not "1111001"; -- output on the 7 seg the number3
when state4 =>
tempC <= "0000000000000000";
tempA <= "0000";
tempB <= "0000000000000000";
tempD <= "0000000000000000";
tempE <= "0000000000000000";
tempF <= "0000000000000000";
nextstate <= state0;
aout <= not "0110011";
end case;
end process;
end behavioral;