I'm trying to implement a linked list in MIPS and I also need to allocate memory for it. In every example I see, they assume that the first element in the list is on certain register, but they don't actually explain how to do it realistically.
I tried this, but it says "store address not aligned on word boundary 0x10040319"
# Allocate memory with syscall 9
li $v0, 9
addi $a0, $zero, 8 # Reserve 8 bytes, 4 for int data, 4 for pointer to next
syscall
# Make $t0 point to the beginning of the reserved memory?
add $t0, $v0, $zero
# Create linked list node
addi $t1, $zero, 10 # $t1 has the int data
sw $t1, 0($t0) # $t1 is now node->data
sw $zero, 4($t0) # node->next is NULL
So I have two questions here, but they are related to each other. One is how to properly allocate memory with syscall 9, and the other one is how to reference it so it can be used in a linked list (I actually need to implement a sorting algorithm using linked lists, because I need to be able to sort any number of elements (not a fixed number) and this is step -1 haha). Thanks.
Oh god, apparently it was the simulator they uploaded for the assignment.
I downloaded the most recent version of Mars MIPS from the official website and it worked. Well, this is awkward.
Related
I'm studying computer architecture. I'm confused about some quiz.
when executing n instructions in load-store arch.
lw $t0, 32($s3)
add $t0, $s2, $t0
sw $t0, 48($s3)
then what is number of memory access, and number of instruction access?
I think num of memory access is 2 and num of instruction access is 3. Is it right?
Yes it's right, Just for the sake of understanding it better here is some explanation.
MIPS using load word instruction lw to read data word from memory into register and
store word sw to write a word in memory.
lw $t0, 32($s3)
This load a word from memory into register $t0
add $t0, $s2, $t0
This means you are on the register side no memory involved.
sw $t0, 48($s3) This store a word in memory.
You are using 3 instruction which two of them involve with memory access
I understand that registers in memory are 32 bits. I also understand that lb will load contents from memory into the lower 8 bits of a register, and that if I did
lb $t1, $a3
lb $t1, 4($a3)
The second lb command will overwrite the contents loaded in the first. However, is there a way to write into the second byte of a register (loading from a different part in memory, so not two bytes right next to each other) and preserve the information of the first byte?
I am assuming what you want to use here is lbu (load byte unsigned) and not lb because you don't want the register to be sign extended (e.g. copying the byte AA in the register will result in 000000AA, and not FFFFFFAA).
If you want to write to the second byte of a register you can first use lbu to load the byte from memory to another register, then shift left 8 bits, and addu it to the original register.
For example:
lbu $t1, $a3 # 0x000000AA
lbu $t2, 4($a3) # 0x000000BB
sll $t2, $t2, 8 # 0x000000BB -> 0x0000BB00
addu $t1, $t1, $t2 # 0x000000AA + 0x0000BB00 = 0x0000BBAA
I am working with MIPS Assembly in the Mars simulator and I am attempting to set it up so that I can enter any 2-digit number (ex: 24) into the Keyboard and Display MMIO Simulator and then take it from MMIO addresses and put it into my registers for manipulation. This technique will use polling, which I understand to some degree.
I can load individual characters and place their ascii value into my registers using the following code (inside .text):
main:
lui $t0, 0xFFFF #$t0 = 0xFFFF0000
poll: # polling procedure
lw $t1, 0($t0)
andi $t1, $t1, 0x0001
beq $t1, $zero, poll
lw $a0, 4($t0) # load word into register $a0
Is it possible in this case for MMIO to treat the input as an immediate and to take in two at once? If not, then are there any known workarounds to this? Thanks.
How does 'alignment of memory operands' help MIPS to be pipelined?
The book says:
Fourth, as discussed in Chapter 2, operands must be aligned in memory. Hence,
we need not worry about a single data transfer instruction requiring two data
memory accesses; the requested data can be transferred between processor and
memory in a single pipeline stage.
I think I understand that one data transfer instruction does not require two or more data memory aaccesses.
However, I am not sure what does it have to do with the alignment of memory operands.
Thanks, in advance!
The lw instruction requires that the memory address be word aligned.
Therefore, to access an unaligned word, one would need to access the two word boundaries that the required word intersects and mask out the necessary bytes.
For example, suppose you desire to load a word stored at address 0x2. 0x2 is not word aligned, so you would need to load the half word stored at 0x2 and the half-word stored at 0x4.
To do so, one might write:
lh $t0 2($zero)
lh $t1 4($zero)
sll $t1 $t1 16
or $t2 $t0 $t1
This only gets more complicated if you want to load for example a word stored at address 0x3:
# load first byte
lb $t0 3($zero)
# load second word, mask out first 3 bytes
lw $t1 4($zero)
lui $t2 0x0000FFFF
ori $t2 $t2 0xFFFFFFFF
or $t1 $t1 $t2
# combine
sll $t1 $t1 8
or $t2 $t0 $t1
So, it can be seen that the requirement for word alignment doesn't help MIPS to be pipelined, but rather that access to unaligned words requires excess memory accesses — this is a limitation of the ISA.
I have a function that takes a memory address as $a0 and I access the (variable) number of words by using x($a0), where x is multiples of 8. I need to store these in the $sp register so I can use the $a0 register for passing arguments to other functions. Completely new to MIPS assembly, so any pointers here would help!
Multiples of 8 i assume you are using mips-64
first u make a loop and increment a0 by 8 each time:
loop: lw $t0, 0($a0) ;fetch data and store in t0
addi $sp,$sp,-8 ;increase stack
sw $t0, 0($sp) ;store data fetched
addi $a0,$a0,8 ;increment a0 to go to next entry
;here you check that you haven't reached x yet
;let's say 8*x+$a0(initial) is stored in $t1 (this is easy to do just use sll by 3 to multiply by 8 then add a0 before loop)
bne $a0,$t1,loop
;now you can use $a0