FMAD format in CUDA - cuda

Question

I cannot find a document that explains the the following instruction format in CUDA
FMAD R6, -R6, c [0x1] [0x1], R5;
What is the format (source, destination, ...) and what is that -R6?

Answer 1

The PTX reference guide describes fma as follows
fma.rnd{.ftz}{.sat}.f32 d, a, b, c;
fma.rnd.f64 d, a, b, c;
performs
d = a*b + c;
in either single or double precision.
You are looking at disassembled SASS, the instruction set references for that show FMAD as being the (non IEEE 754 compliant) single precision form from the GT200 instruction set. That is a little bit problematic, because I don't presently have a toolchain which supports that deprecated instruction set. However, if I use the Fermi instruction set instead and compile this kernel:
__global__ void kernel(const float *x, const float *y, float *a)
{
float xval = x[threadIdx.x];
float yval = y[threadIdx.x];
float aval = -xval * xval + yval;
a[threadIdx.x] = aval;:
}
I get this SASS:
code for sm_20
Function : _Z6kernelPKfS0_Pf
.headerflags #"EF_CUDA_SM20 EF_CUDA_PTX_SM(EF_CUDA_SM20)"
/*0000*/ MOV R1, c[0x1][0x100]; /* 0x2800440400005de4 */
/*0008*/ S2R R3, SR_TID.X; /* 0x2c0000008400dc04 */
/*0010*/ MOV32I R5, 0x4; /* 0x1800000010015de2 */
/*0018*/ IMAD.U32.U32 R8.CC, R3, R5, c[0x0][0x20]; /* 0x200b800080321c03 */
/*0020*/ IMAD.U32.U32.HI.X R9, R3, R5, c[0x0][0x24]; /* 0x208a800090325c43 */
/*0028*/ IMAD.U32.U32 R6.CC, R3, R5, c[0x0][0x28]; /* 0x200b8000a0319c03 */
/*0030*/ LD.E R0, [R8]; /* 0x8400000000801c85 */
/*0038*/ IMAD.U32.U32.HI.X R7, R3, R5, c[0x0][0x2c]; /* 0x208a8000b031dc43 */
/*0040*/ IMAD.U32.U32 R4.CC, R3, R5, c[0x0][0x30]; /* 0x200b8000c0311c03 */
/*0048*/ LD.E R2, [R6]; /* 0x8400000000609c85 */
/*0050*/ IMAD.U32.U32.HI.X R5, R3, R5, c[0x0][0x34]; /* 0x208a8000d0315c43 */
/*0058*/ FFMA.FTZ R0, -R0, R0, R2; /* 0x3004000000001e40 */
/*0060*/ ST.E [R4], R0; /* 0x9400000000401c85 */
/*0068*/ EXIT; /* 0x8000000000001de7 */
..................................
Note that I also have the negated register in the FFMA.FTZ arguments. So I would guess that your:
FMAD R6, -R6, c [0x1] [0x1], R5;
is the equivalent of
R6 = -R6 * const + R5
where c [0x1] [0x1] is a compile time constant, and that the GPU has some sort of instruction modifier which it can set to control negation of a floating point value as part of a floating point operation without explicitly twiddling the sign bit of the register before the call.
(I look forward to #njuffa tearing this answer to shreds).