Missing build file during sbt run - chisel

Question

I added "--backend" and "v" to my chiselMainTest list, and although I am getting verilog output, I am also getting a build error:
In file included from ./vpi.cpp:1:
./vpi.h:4:10: fatal error: 'vpi_user.h' file not found
#include "vpi_user.h"
^
1 error generated.
A complete listing of the sbt run follows:
BigKiss:chisel mykland$ sbt run
[info] Set current project to chisel (in build file:/Users/mykland/work/chisel/)
[info] Compiling 1 Scala source to /Users/mykland/work/chisel/target/scala-2.10/classes...
[warn] there were 38 feature warning(s); re-run with -feature for details
[warn] one warning found
[info] Running mainStub
[info] [0.056] // COMPILING < (class lut3to1_1)>(0)
[info] [0.078] giving names
[info] [0.088] executing custom transforms
[info] [0.089] adding clocks and resets
[info] [0.093] inferring widths
[info] [0.108] checking widths
[info] [0.110] lowering complex nodes to primitives
[info] [0.113] removing type nodes
[info] [0.117] compiling 84 nodes
[info] [0.117] computing memory ports
[info] [0.117] resolving nodes to the components
[info] [0.133] creating clock domains
[info] [0.134] pruning unconnected IOs
[info] [0.136] checking for combinational loops
[info] [0.139] NO COMBINATIONAL LOOP FOUND
[info] [0.149] COMPILING <lut3to1_1 (class lut3to1_1)> 0 CHILDREN (0,0)
In file included from ./vpi.cpp:1:
./vpi.h:4:10: fatal error: 'vpi_user.h' file not found
#include "vpi_user.h"
^
1 error generated.
[info] [0.666] g++ -c -o ./vpi.o -I$VCS_HOME/include -I./ -fPIC -std=c++11 ./vpi.cpp RET 1
[error] lut3to1_1.scala:58: failed to compile vpi.cpp in class mainStub$
Re-running Chisel in debug mode to obtain erroneous line numbers...
[info] [0.030] // COMPILING < (class lut3to1_1)>(0)
[info] [0.035] giving names
[info] [0.037] executing custom transforms
[info] [0.037] adding clocks and resets
[info] [0.038] inferring widths
[info] [0.045] checking widths
[info] [0.046] lowering complex nodes to primitives
[info] [0.047] removing type nodes
[info] [0.049] compiling 84 nodes
[info] [0.049] computing memory ports
[info] [0.049] resolving nodes to the components
[info] [0.055] creating clock domains
[info] [0.055] pruning unconnected IOs
[info] [0.056] checking for combinational loops
[info] [0.056] NO COMBINATIONAL LOOP FOUND
[info] [0.060] COMPILING <lut3to1_1 (class lut3to1_1)> 0 CHILDREN (0,0)
In file included from ./vpi.cpp:1:
./vpi.h:4:10: fatal error: 'vpi_user.h' file not found
#include "vpi_user.h"
^
1 error generated.
[info] [0.535] g++ -c -o ./vpi.o -I$VCS_HOME/include -I./ -fPIC -std=c++11 ./vpi.cpp RET 1
[error] lut3to1_1.scala:58: failed to compile vpi.cpp in class mainStub$
[error] (run-main-0) Chisel.ChiselException: failed to compile vpi.cpp
Chisel.ChiselException: failed to compile vpi.cpp
at mainStub$.main(lut3to1_1.scala:58)
[trace] Stack trace suppressed: run last compile:run for the full output.
java.lang.RuntimeException: Nonzero exit code: 1
at scala.sys.package$.error(package.scala:27)
[trace] Stack trace suppressed: run last compile:run for the full output.
[error] (compile:run) Nonzero exit code: 1
[error] Total time: 9 s, completed Oct 4, 2015 6:33:30 PM
BigKiss:chisel mykland$
A complete listing of my source code follows:
import Chisel._
class lut3to1_1 extends Module
{
val io = new Bundle
{
val config = UInt(INPUT, 8)
val a = Bool(INPUT)
val b = Bool(INPUT)
val c = Bool(INPUT)
val out = Bool(OUTPUT)
}
io.out := (io.config(0) & !io.a & !io.b & !io.c) |
(io.config(1) & io.a & !io.b & !io.c) |
(io.config(2) & !io.a & io.b & !io.c) |
(io.config(3) & io.a & io.b & !io.c) |
(io.config(4) & !io.a & !io.b & io.c) |
(io.config(5) & io.a & !io.b & io.c) |
(io.config(6) & !io.a & io.b & io.c) |
(io.config(7) & io.a & io.b & io.c)
}
class lut3to1_1_Tests(c: lut3to1_1) extends Tester(c)
{
for ( config <- 0 to 255 )
{
poke( c.io.config, config )
for ( bits <- 0 to 7 )
{
val bitA = bits & 1
val bitB = (bits >> 1) & 1
val bitC = (bits >> 2) & 1
poke( c.io.a, bitA )
poke( c.io.b, bitB )
poke( c.io.c, bitC )
step( 1 )
val result0 = ~bitA & ~bitB & ~bitC & (config & 1)
val result1 = bitA & ~bitB & ~bitC & ((config >> 1) & 1)
val result2 = ~bitA & bitB & ~bitC & ((config >> 2) & 1)
val result3 = bitA & bitB & ~bitC & ((config >> 3) & 1)
val result4 = ~bitA & ~bitB & bitC & ((config >> 4) & 1)
val result5 = bitA & ~bitB & bitC & ((config >> 5) & 1)
val result6 = ~bitA & bitB & bitC & ((config >> 6) & 1)
val result7 = bitA & bitB & bitC & ((config >> 7) & 1)
val result = result0 | result1 | result2 | result3 |
result4 | result5 | result6 | result7
expect( c.io.out, result )
}
}
}
object mainStub
{
def main( args: Array[String] ): Unit =
{
chiselMainTest( Array[String]("--backend", "c", "--backend", "v",
"--compile", "--test", "--genHarness"), () => Module( new lut3to1_1() ) )
{
c => new lut3to1_1_Tests( c )
}
}
}

Answer 1

The missing header file (vpi_user.h) is related to Verilog simulators VPI support, which is the mechanism that Chisel uses to connect your Tester to the Verilog simulator. The current version of Chisel only supports Synopsys VCS as the Verilog simulation tool. There's experimental support for Icarus Verilog (iverilog) version 10.0+, Verilator, Modelsim and Questasim in my fork of Chisel (available here) . Unfortunately I haven't had time to thoroughly test the changes and make a pull-request to the main repository, but you can try it and see if it works for you.

Answer 2

This command is to generate verilog for testbenches simulator.
If you just want to generate verilog for synthesis, simply add chiselMain() function in your main() like it :
object mainStub
{
def main( args: Array[String] ): Unit =
{
chiselMainTest( Array[String]("--backend", "c",
"--compile", "--test", "--genHarness"), () => Module( new lut3to1_1() ) )
{
c => new lut3to1_1_Tests( c )
}
chiselMain(args, () => Module(new lut3to1_1()))
}
}
You will get a synthetizable verilog file named lut3to1_1.v