Vhdl Multiplier usage too low - fft

Question

My design utilizes the Spartan 3E XC35100E device. I can use a total of 4 MUX. However, despite using 3 * signs and a FFT block (which also uses 3 MUX), the design summary specifies that I only use 1 MUX. Even when I use CLB logic in place of MUX for the FFT block, the design summary is the same.
Implementation and simulation are able to take place without any problems. So, why is the number of MUX I use so low? Any help would be greatly appreciated.
relevant libraries, port maps and signal declarations are excluded for brevity.
process (clk)
variable fsm : integer range 0 to 3:= 0;
variable i : integer range 0 to 127:= 0;
begin
if rising_edge(clk) then
if fsm = 0 then
tasiyici <= STD_LOGIC_VECTOR(to_signed(sample_1(i)* sample_2(i) , 16));
--sample1 and sample 2 are arrays with constant values
fsm := fsm +1;
elsif fsm = 1 then
wea_select <= '0';
wea_ram<= "1";
ram_write <= '0';
dina <= STD_LOGIC_VECTOR(tasiyici(15 downto 8));
mult_out<= STD_LOGIC_VECTOR(tasiyici(15 downto 8));
fsm := fsm +1;
elsif fsm = 2 then
address_write <= std_logic_vector(unsigned(addra) + 1);
wea_ram<= "0";
i := i+1 ;
if i=128 then
fsm:=3;
ram_write <= '1';
wea_select <= '1';
else
fsm := 0;
end if;
end if;
end if;
end process;
----FFT process---
process(clk)
variable fsm : integer range 0 to 7:= 0;
variable i : integer range 0 to 128;
variable counter : integer range 0 to 2:= 0;
variable j : integer range 0 to 512;
begin
if rising_edge(clk) then
if fsm = 0 then -- ram_write is control
if ram_write = '1' then
wea_fft <= "0";
fsm:= 1;
end if;
elsif fsm = 1 then --process start (pulse)
start <= '1';
fwd_inv_we <= '1';
fsm := fsm +1;
elsif fsm = 2 then
start <= '0';
fwd_inv_we <= '0';
fsm := fsm +1;
elsif fsm =3 then --128 cycle send data from douta to xn_re
if i= 128 then
fsm := fsm +1;
else
xn_re <= douta;
address_read <= std_logic_vector(unsigned(addra) + 1);
i:=i+1;
fsm := 3;
end if;
elsif fsm =4 then --all data sent. process complete
if done = '1' then --wait for done finish 3 clk cycle, then unload
if counter= 2 then
fsm := fsm +1;
else
counter := counter +1;
fsm :=4;
end if;
end if;
elsif fsm =5 then
counter := 0;
unload <= '1';
fsm := fsm +1;
fft_data_ready <= "1";
wea_fft<= "1";
elsif fsm =6 then --wait 512 clk cycle to read all outputs
unload <= '0';
wea_fft<= "0";
if dv = '1' then
fft_output <= std_logic_vector(signed(xk_re(15 downto 4))*signed(xk_re(15 downto 4))
+signed(xk_im(15 downto 4))*signed(xk_im(15 downto 4)));
if j=512 then
fsm:=fsm+1;
else
j:=j+1;
fsm:=6;
end if;
else
fsm:=6;
end if;
end if;
end if;
end process;

Answer 1

It seems like your design has simply been optimized.
You should check the RTL that is synthesized to check that your design has been synthesized the way that you wanted