MIPS: Code Scheduling To remove Stalls - mips

I have the following MIPS code:
addi $s1, $0, 10
lw $t0, 4($s0)
srl $t1, $t0, 1 [STALL becausee $t0 depends on lw's $t0]
add $t2, $t1, $s1 [STALL because $t1 depends on srl's $t1]
sw $t2, 4($s0)
How can I rearrange it to avoid any stalls. I see that all the 2 to 5 line's sequence can't change. We can only move the first line in between srl and add OR lw and srl. Any ideas?

There are 4 read after write (RAW) dependencies in your code: addi->add, lw->srl, srl->add, add->sw. These can't be fixed as you pointed out.
What you can do is move the addi instruction. I would think the best place to move this instruction would be after the lw because in the MIPS architecture all load instructions use a load delay slot. This means that the instruction immediately after the load does not have access to the contents of the load. If you are using this code in a simulator such as spim or MARS this may not be simulated, but assuming you mean to use the loaded value of $t0 in the srl instruction, your assembly above is actually incorrect. For this to work, there should be a nop in between the lw and srl.
For that reason, it would be best to move the addi in between the lw and srl so as to utilize the lw load delay slot.

Related

Dual-issue scheduling in MIPS

Here are the MIPS code:
Loop: lw $t0, 0($s1) # $t0=array element
addu $t0, $t0, $s2 # add scalar in $s2
sw $t0, 4($s1) # store result
addi $s1, $s1,–4 # decrement pointer
bne $s1, $zero, Loop # branch $s1!=0
After scheduling, we can pack them like below:
Why addi instruction can move before the sw instruction?
They both use the $s1 register.
Before scheduling in the first iteration,we will get 0($s1)-> $t0, 4($s1)<- $t0+$s2.
However the scheduling result may be 0($s1)-> $t0, 0($s1)<- $t0+$s2
There are obviously different.
What I guess there is a magic in pipeline.
I don't know what the name is,so I call it "anti-data hazard".
Since addi instruction will write back in the 5th stage(WB), we could use the data hazard to make the sw instruction get the old data address($s1) in stage3.
(sw instruction will not trigger forwarding)
Is my guess right?Please tell me.

MIPS OR logic and bit shifting

If I call the two MIPs instructions
lui $s0, 0x9344 //Load upper immediate
ori $s0, $s0, 0xB01A //Logical Or Immediate
what is the value in $s0? Everytime I work it out I get the value 0x44B01A which I think is wrong.

MIPS store word/load word

have a really basic question here.
Can a register have both a value and an address. As in assuming i want to swap between values: 5 stored in t0 and 7 stored in t1
does this code work:
sw $t0, 0($t0)
sw $t1, 0($t1)
lw $t1, 0 ($t0)
lw $t0, 0 ($t1)
Sorry this might sound stupid
Not really for all values, as sw and lw need proper alignment (valid addresses should be multiple of 4).
That is, your code would only work for values multiple of 4, and anyways it would be a bad idea to do so, because you would be basically write garbage on whichever address you are pointing at.
To swap registers without overwriting a third register you can use the following trick:
xor $t0, $t0, $t1
xor $t1, $t0, $t1
xor $t0, $t0, $t1

Using lw on address of $ra

Assuming we have something of this sort in MIPS
jal F
F: lw $t1, 0($ra)
lw $t2, 8($ra)
What would we have in $t1 and $t2?
Will $t1 have the instruction code of F??
Say X is the address of label F
when jal is called $ra will hold X
you load what is on $ra to $t1 which is the binary machine laguage of the instruction at X
then you load what is 2 words lower (8) which is here not specified in your code, you need to show a 4th line of code to tell you =)

MIPS, using a while loop to calculatethe sum of odd integers 1-9

The following is my code in MIPS to calculate the sum of odd integers using a while loop.
.data
num: .space 4
.text
.globl main
main:
li $t1, 1
li $t2, 9 # make $t2 9 to break the loop
li $t3, 1
loop:
beq $t3, 11, Exit # check to see if $t3 = 11 if so exit
addi $t3, $t3, 2 # change $t3 to next odd number by adding 2
add $t1, $t1, $t3 # add $t3 to $t1 (1+3,...3+5...etc...)
j loop #jump back to the start of the loop
Exit:
li $v0, 1 # system call code to print an int
lw $a0, num # address of int to print
syscall # print the int
jr $ra #exit
This is my first real experience with MIPS and I'm not sure what is going wrong in this code. I put the print inside the while loop to see if it was ever calculating, but the result is always 1.
So, my result at the end is just 111111.
Edit: Removed the prints inside of the loop with the same result.
And OS is Windows 7 64x
Update: Having num as a variable was over complicating things. Code has been revised as follow and works. Thank you for the help!
enter code here
.data
.text
.globl main
main:
addi $t1, $0, 1
addi $t2, $0, 3
loop: bge $t2, 11, Exit # check to see if $t3 >= 11 if so exit
add $t1, $t1, $t2 # add $t2 to $t1 (1+3,...3+5...etc...)
addi $t2, $t2, 2 # change $t2 to next odd number by adding 2
j loop #jump back to the start of the loop
Exit:
li $v0, 1 # system call code to print an int
move $a0,$t1 # address of int to print
syscall # print the int
jr $ra #exit
la $t1, num
You're clearly getting into trouble here, since you're overwriting your accumulator with the address of num every time you're making the syscall. You're losing the current state of your calculation each time.
You'll need to either save your registers, or simply use different ones. Since I don't know what OS it is that you're using, I don't know if you more generally need to save registers over a syscall, but that could also be a source of errors.
I did similar problems for an architecture class and this seemed to be a recurrent problem among all students. When facing problems similar to this our professor's recommendation was to use a different register to temporarily store the register's address to avoid overwriting other desired values from our most commonly used regs.