VHDL Full adder test bench output U - output

Question

I'm a vhdl newbie.i wrote codings for a full adder using only AND and OR gates. I created a testbench to test my code and had it configured to stimulate all of eight logic combinations for A,B and Cin. when i run the simulation wave forms are correct for the inputs but the sum out put(H in my case) shows just "U".any ideas please.
library ieee;
use ieee.std_logic_1164.all;
--This program describes behaviour of a full adder constructed using
-- AND and OR gates. It employs component method which describes behaviour of
--AND,OR and NOT gates and use them to build the final object
--Entity description of the full adder
entity full_add is
port (a,b,c:IN BIT; h:OUT BIT);
end entity full_add;
--Description the 3 input And Gate
entity And2 is
port (j,k,l:in BIT; m:out BIT);
end entity And2;
architecture ex1 of And2 is
begin
m <= (j AND k AND l);
end architecture ex1;
--Description of the four input OR gate
entity Or2 is
port (d,e,f,g:IN BIT; h:OUT BIT);
end entity Or2;
architecture ex1 of Or2 is
begin
h <= (d or e or f or g);
end architecture ex1;
--Description of the NOT gate
entity Not1 is
port(x:in BIT; y:out BIT);
end entity Not1;
architecture ex1 of Not1 is
begin
y <= not x;
end architecture ex1;
--Components and wiring description
architecture netlist of full_add is
signal s,u,v,s2,u2,v2,w2:BIT;
begin
g1:entity WORK.Not1(ex1) port map(a,s);
g2:entity WORK.Not1(ex1) port map(b,u);
g3:entity WORK.Not1(ex1) port map(c,v);
g4:entity WORK.And2(ex1) port map(s,u,c,s2);
g5:entity WORK.And2(ex1) port map(s,b,v,u2);
g6:entity WORK.And2(ex1) port map(a,u,v,v2);
g7:entity WORK.And2(ex1) port map(a,b,v,w2);
g8:entity WORK.Or2(ex1) port map (s2,u2,v2,w2,h);
end architecture netlist;

Answer 1

You are going to have to debug the implementation : this will be quite a good exercise in using the simulator!
You see that "H" has value 'U' but you don't yet know why. Trace all the drivers of H back : in the posted code I can only see one, which is derived from inputs S2, U2, V2, W2.
In the simulator, add these signals to the Wave window and re-run the simulation : is one of them stuck at 'U'? If so, trace that signal back to find out why. If they all have valid values, that points to something else driving 'U' onto signal H.
Learn the "Drivers" command for your simulator (i.e. find and read the manual!) to identify all the signals driving H, and their values at a given time. There may be a driver in the (hidden to us) testbench. If so, change its driving value (perhaps with an H <= 'Z';" assignment) and re-run the simulation.
Essentially : learn and practice basic simulation debugging skills : one of these skills is likely to resolve the problem. And edit the question with what you have learned from them : if the problem persists, these results will point closer to it.