I was asked the following question on an assignment, but I'm not sure if I did it correctly.
"What is the largest memory space (i.e. program) that can be addressed by processors with the following number of address bits?
(c) 24 bits"
I put 011111111111111111111111 (0 followed by 23 1s). Is this correct? If not, how do I find the answer to this question? You can use a different amount of bits for an example if you want to. Thanks for any help.
No 011111111111111111111111 is not the correct answer. I'm assuming that you were calculating the largest number that can be represented by a signed 24 bit integer.
Memory address would be always unsigned so the answer is the number items that can be represented in 24 bits, which is 2^24 or 1000000000000000000000000 which is 1 followed by 24 zeros (assuming that I counted correctly) - since the address range includes 0 and goes to 1111111111111111111111 (24 1's).
2^N bytes, where N is number of bits in the address space.
For example, the 8088 processor had a 20 bit address space and so it could address 2^20 bytes = 1 MB.
Address space is unsigned so N is full number of bits, not number of bits minus 1.
An address in programming is usually something that represents a location in memory.
You can always represent as many locations as there are unique numbers.
How many locations can you address with a range from 1 to 10? 10.
How many locations can you address with a range from 1 to 2^24? 2^24.
So you can represent 2^24 locations and you didn't answer correctly.
You're on the wrong track.
Memory addresses are unsigned, so the size of the address space is 2^24 bytes, or 16Mb.
If you had 2 bits you could go from 00 to 11, 00, 01, 10, 11, four addresses. Four is 1 with two zeros 0. Two address bits one with two zeros is the number of addresses or 2 to the power 2. 3 bits 0b1000 or 8 addresses 2 to the power 3, 4 bits 0b10000 or 16 addresses, 2 to the power 4 and so on to whatever number of bits you want.
Related
Let's say that a jump instruction is located at memory address 0x20CE88C0. What is the highest (i.e., greatest) 32-bit memory address to which this jump can transfer control?
I know the highest address can be 2^26, but I see others saying 2^28. I don't understand the difference. Why is 2^28?
The J-Type instruction is very simple:
opcode target
6 26 // field size, as bit count
target := instruction[25:0]
JumpAddr := { PC+4[31:28], target, 2'b0 }
PC := JumpAddr
This is the description in the MIPS Green Sheet / Quick Reference Data. Though a somewhat funny notation (some kind of RTL), it tells us what we need to know about the possible range of jump instructions, by telling us how the processor decodes the J-Type instructions.
What this says is that the current PC+4 provides the upper 4 bits of the new PC address. Then the address field, sometimes called immediate otherwise called target — either way is 26 bits wide — provides the next 26 bits, and then 00 are the next 2 bits, for a total of 32 bit value for the next PC.
So, with that information, you can compute or form the largest possible address that can be reached from the given PC. Take PC+4's top 4 bits, and then (string/concatenate onto those 4 bits) a 26 bit max value — its 26 bits unsigned, so 26 all 1's is the max value — then concatenate a 00 (two zero bits) and to make the 32-bit value of the exact address of the maximum addressable location from the j/jal starting at the given PC.
This is some more clarification to the question that was already answered some time ago here: biggest integer that can be stored in a double
The top answer mentions that "the largest integer such that it and all smaller integers can be stored in IEEE 64-bit doubles without losing precision. An IEEE 64-bit double has 52 bits of mantissa, so I think it's 2^53:
because:
253 + 1 cannot be stored, because the 1 at the start and the 1 at the end have too many zeros in between.
Anything less than 253 can be stored, with 52 bits explicitly stored in the mantissa, and then the exponent in effect giving you another one.
253 obviously can be stored, since it's a small power of 2.
Can someone clarify the first point? What does he mean by that? is he talking about for example if it were a 4 bit number 1000 + 0001, you can't store that in 4 bits? 253 is just the first bit 1 and the rest 0's right? how come you can't add a 1 to that without losing precision?
also, "The largest integer such that it and all smaller integers can be stored in IEEE". Is there some general rule such that if I wanted to find the largest n bit integer such that it and all smaller integers can be stored in IEEE, could I simply say that it is 2n? example if I were to find the largest 4 bit integers such that it and all integer below it can be represented, it would be 2^4?
is he talking about for example if it were a 4 bit number 1000 + 0001, you can't store that in 4 bits?
No, he is saying that you can't store that in 3 bits. Using the usual binary notation.
253 is just the first bit 1 and the rest 0's right?
Yes, and so are 1, 2, 4, …, 253, 254, 255, …, 2123, 2124, … and also 0.125.
This is floating-point we are talking about. 253 is just an implicit 1 with all explicit significand bits 0, yes, but it is not the only number with this property. The crucial property is that the ULP for representing 253 is 2. So 253 can be represented as all powers of two that are in range, and 253+1 cannot because the ULP is too large in that neighborhood.
also, "The largest integer such that it and all smaller integers can be stored in IEEE". Is there some general rule such that if I wanted to find the largest n bit integer such that it and all smaller integers can be stored in IEEE, could I simply say that it is 2n?
Yes, in binary IEEE 754 floating-point, all “largest integer such that it and all smaller integers can be stored” are powers of two, and specifically 2n where n is the significand's width (counting the implicit bit).
How many bits are required to store three different values?
My guess is 8 times 3 = 24 bits.
I'm confused because I learned in class that a 8-bit byte can only hold a value between 0 and 255. Does this mean to store a value above 255 we need more than 8 bits?
A bit is either 0 or 1. So it can store 2 values.
Two bits can store 2*2 values, 4.
Three bits can store 2*2*2 values, 8.
And so on.
So to store 3 values, you need at least two bits.
You need more than 8 bits to store more than 256 values, yes, because 2^8 is 256.
TL;DR: two digits.
In any number base system, the number of values that can be held by a single digit is equal to the base number, so for the regular base-10 number system, that would be 10 (0 through 9). To hold higher numbers, you give yourself more digits: this would be the ones place, tens place, hundreds place, etc you learned in school.
Once you start giving yourself more digits, then it's just a matter of combinations: in a two-digit base-10 number, how many combinations are there? 00 through 99, so 100; with three digits, 000 through 999, so 1000.
The name bit is nothing more than the special name given to the digit in base-2 (otherwise known as binary). It can hold exactly two values, 0 and 1. To get more, you'd have to give yourself another digit, e.g., the ones place, the twos place. And even more digits: the fours place, the eights place, etc. Again, it's nothing but combinatory math. Two base-2 digits (or binary digits, or bits) can hold values 00 through 11, so 4; with three bits 00 through 111, so 8; with four bits 00 through 1111, so 16; with eight (a byte) 00000000 through 11111111, so 256.
So, in order to hold three values - e.g., 0 1 and 2 base-10 - you'd need two digits: 00 01 and 10 binary.
Please have a look at this Single Cycle Data Path in MIPS. The 26 bits of J type instruction are being Bit Extended to 28. I don't get the point. Shouldn't it be extended to 31 so it makes 32 bits overall. Please help me out to clear the concept.
Thanks
This is really no sign extension. Recall that the instructions in MIPS are 4-byte aligned.
This means that you can start an instruction at addresses which are 0 modulus 4 (i.e. 0, 4, 8, 12, ...)
Now, doing a shift left of 2 two bits is like multiplying by 4, which yields numbers which are always 0 modulus 4.
The actual address will be formed with:
- the 4 most significant bits of the nPC (that is PC+4) (lets call them PPPP)
- the 26 bits of the address field specified in the instruction, (lets call them AAA....AA)
- 00 as the two least significant bits (which yields the required instruction alignment)
Thus the address will be (binary) PPPPAAAAAAAAAAAAAAAAAAAAAAAAAA00
I read this:
Recall that paging is implemented by
breaking up an address into a page and
offset number. It is most efficient to
break the address into X page bits and
Y offset bits, rather than perform
arithmetic on the address to calculate
the page number and offset. Because
each bit position represents a power
of 2, splitting an address between
bits results in a page size that is a
power of 2.
I don't quite understand this answer, can anyone give a simpler explanation?
If you are converting a (linear) address to page:offset, you want to divide the address by the page size and take the integer answer as the page, and the reminder as the offset.
This is done using integer division and modulus (MOD, "%") operators in your programming language.
A computer represents an address as a number, stored as binary bits.
Here's an example address: 12 is 1100 in binary.
If the page size is 3, then we'd need to calculate 12/3 and 12%3 to find the page and offset (4:0 respectively).
However, if the page size is 4 (a power of 2), then 4 in binary is 100, and integer division and modulus can be computed using special 'shortcuts': you can strip the last two binary digits to divide, and you can keep only the last two binary digits for modulus. So:
12/4 == 12>>2 (shifting to remove the last two digits)
12%4 == 12&(4-1) (4-1=3 is binary 11, and the '&' (AND) operator only keeps those)
Working with powers of two leads to more efficient hardware so that's what hardware designers do. Consider a cpu with a 32-bit address, and an n-bit page number:
+----------------------+--------------------+
| page number (n bits) | byte offset (32-n) |
+----------------------+--------------------+
This address is sent to the virtual memory unit, which directly separates the page number and byte offset without any arithmetic operations at all. Ie, it treats the 32-bit value as an array of bits, and has (more or less) a wire running directly to each bit. This allows the memory hardware to extract the page number and byte offset in parallel, without performing any arithmetic operations.
At the same time, this approach requires splitting on a bit boundary, which leads directly to power-of-2 page sizes.
If you have n binary digits at your disposal, then you can encode 2n different values.
Given an address, your description states some bits will be used for the page, and some for the offset. As you're using a whole number of binary bits for the for offset Y, then the page size is naturally a power of 2, specifically 2Y.
Because the representation of the data. The page offset sets the size of the page, and since the data is represented in binary, you will have a number n of bits to define the offset, so you will have pages with a size of 2^n.
Let's suppose you have an address like this 10011001, and you split it in 1001:1001 for page:offset. Since you have 4 bits to define the offset, your page's size is 2⁴.
If it is not exact power of 2 then some memory address will be invalid. eg if the page size is 5 byte then to distinguish each byte we need 3 bit in the offset part of the address. Because using 2 bit only 4 byte can be addressed. But using 3 bit offset for 5 byte page keep two address unused. thats why page size should be .......
since all addresses are in binary and are divided into f and d, f=frame no, d=offset. due to be the size in power of 2 a human no need to go for huge mathematical calculation, just by watching the address bits you can identify the f and d. If page size was 2^n the in physical address last n bits represents the offset and remaining bits represent page numbers.
Hopefully this answer will help you.
I realized what I didn't get was how the page sizes are a power of 2. I found out afterwards:
At the smallest level, the page is 1 bit (0 or 1) and the offset is 1 bit (0 or 1). Combining these together, the page size would be 2 x 2 (or 2^2), because of the number of bits they both have (2 each, so 2 x 2).
Now if the page/offset were larger, then it would be n x n -- n being the number of bits they both have.
The page no. is always in the power of 2 as (2^n).
There are several reasons:
1.The memory address is also in 2^n so it will be more easy to move a page.
2.There are two bits which represent the page:
a.Page no. b.Offset no
So,This is also the reason.
3.Memory is in quantised form like charge(q).