I am simulation the LEON3 with modelsim. After a make vsim I get a do-file I use for calling modelsim.
It gives me a warning message and I don't know if this message now is relevant. Actually I don't know what it means.
# ** Warning: [6] /path/to/lib/tech/ec/orca/orca.vhd(14744): (vcom-1288) VITAL timing generic "tpd_a1_s2" port specification "s2" does not denote a port.
The indicated code:
ENTITY fadsu2 IS
GENERIC(
TimingChecksOn : boolean := TRUE;
XOn : boolean := FALSE;
MsgOn : boolean := TRUE;
InstancePath : string := "fadsu2";
tpd_a0_bco : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_a1_bco : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_b0_bco : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_b1_bco : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_bci_bco : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_con_bco : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_a0_s0 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_a0_s1 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_a1_s0 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_a1_s1 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_a1_s2 : VitalDelayType01 := (0.001 ns, 0.001 ns); -- <--- here
tpd_b0_s0 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_b0_s1 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_b1_s0 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_b1_s1 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_bci_s0 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_bci_s1 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_con_s0 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tpd_con_s1 : VitalDelayType01 := (0.001 ns, 0.001 ns);
tipd_a0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_a1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b0 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_b1 : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_bci : VitalDelayType01 := (0.0 ns, 0.0 ns);
tipd_con : VitalDelayType01 := (0.0 ns, 0.0 ns));
PORT(
a0 : IN std_logic;
a1 : IN std_logic;
b0 : IN std_logic;
b1 : IN std_logic;
bci : IN std_logic;
con : IN std_logic;
bco : OUT std_logic;
s0 : OUT std_logic;
s1 : OUT std_logic);
ATTRIBUTE Vital_Level0 OF fadsu2 : ENTITY IS TRUE;
END fadsu2;
any sugestions?
I happened to have a copy of that source laying around. Comment out the offending line mentioning tpd_a1_s2 and it will compile.
Without modification:
david_koontz#Macbook: ghdl -a fadsu2.vhdl
fadsu2.vhdl:23:7:warning: 's2' is not a port name (in VITAL generic name)
Commenting out the offending generic:
david_koontz#Macbook: ghdl -a fadsu2.vhdl
david_koontz#Macbook:
And it analyzes. (I extracted the entity and architecture pair for fadsu2 from orca.vhd)
The issue is that you have a tpd value (time propagation delay) specified between input a1 and output s2 (tpd_a1_s2), where output port s2 is non-existent.
Related
I'm doing this question with Pascal (Google Kick Start 2020 Round A - Workout) and I ran into a problem that doesn't make any sense at all. Here is a part of my program:
var N,K,i,max,max1 : longint;
M : array [1..100000] of longint;
A : array [1..99999] of longint;
begin
readln(N,K);
for i := 1 to N do
read(M[i]);
for i := 1 to N-1 do A[i] := M[i+1]-M[i];
max := 0;
for i := 1 to N-1 do
if A[i] >= max then
begin
max := A[i];
max1 := i;
end;
writeln('max = ',max); writeln('max1 = ',max1);
readln; readln;
end.
So first I type in all the input data which are:
5 6 and
9
10
20
26
30.
When I run the program, the value of max is 10 and the value of max1 is 2.
But when I change the way max gets its value and totally did nothing with max1, the program becomes like this:
uses crt;
var N,K,i,max,max1 : longint;
M : array [1..100000] of longint;
A : array [1..99999] of longint;
begin
readln(N,K);
for i := 1 to N do
read(M[i]);
for i := 1 to N-1 do A[i] := M[i+1]-M[i];
max := 0;
for i := 1 to N-1 do
if A[i] >= max then
begin
max := i;
max1 := i;
end;
writeln('max = ',max); writeln('max1 = ',max1);
readln; readln;
end.
I run the program, and suddenly both the values of max and max1 are 4. How can this happen? Should I delete Pascal?? By the way if you can't install Pascal for some reasons then go to this link:https://www.onlinegdb.com/, select Pascal language and paste my program. Thanks for helping me!
I am coding a 16-bit CPU for a school project and I've run into an issue that has dumbfounded me. The first three steps of my clock cycle are naturally to increment the program counter and load a new instruction into the instruction register. So the problem; the value in the program counter increments as expected but stalls at 6 for several cycles then picks up again and stalls at 12 for several more, again at 18 and then 24, this is as far as I've let it run, I assume it'll persist at succeeding multiples of six. I dunno if it is something to do with the way VHDL treats signed values, I edited the ALU code to achieve this by adding one to the Program Counter value instead of incrementing but there was no change, I changed the ALUs representation of the values to unsigned but that didn't help and I honestly cannot see why it would. My code is as follows:
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CPU_1 is
port( prim_clk : in std_logic;
achtung : out std_logic_vector(15 downto 0) ;
HEX0, HEX1, HEX2 : out std_logic_vector(6 downto 0));
end CPU_1;
Architecture behaviour of Nandos is
signal sys_clk, clk, cu_s, cu_e: std_logic;
signal step : std_logic_vector(5 downto 0);
signal acc_ena, acc_set, pc_set, pc_ena: std_logic := 'Z';
signal data_bus, alu_acc : std_logic_vector(15 downto 0);--M_addr_bus,
component Clock
port( clk : in std_logic; --50 MHz
clk_s : out std_logic;--set data clk
clk_e : out std_logic);--enable data(on bus) clk
end component;
component Control_Unit
port( sys_clk, clk_s, clk_e : in std_logic;
acc_ena, acc_set, pc_set, pc_ena: out std_logic;
stepp : out std_logic_vector(5 downto 0));
end component;
component program_Counter
port( clk: in std_logic;
set, en : in std_logic;
pc_in : in std_logic_vector(15 downto 0);
pc_out : out std_logic_vector(15 downto 0));
end component;
component ALU
port( clk: in std_logic;
d1 : in std_logic_vector(15 downto 0);
d3 : out std_logic_vector(15 downto 0));
end component;
component accumulator
port( clk: in std_logic;
frm_ALU: in std_logic_vector(15 downto 0);
acc_set, acc_ena : in std_logic;
to_bus : out std_logic_vector(15 downto 0));
end component;
begin
HEX2(5 downto 0) <= step;--serves to demonstrate on the board that it is running
achtung <= data_bus;--debug what is on the bus
clk0 : Clock port map(prim_clk, cu_s, cu_e);
cu0 : Control_Unit port map(prim_clk, cu_s, cu_e, acc_ena, acc_set, pc_set, pc_ena, step);
p_c : program_Counter port map(prim_clk, pc_set, pc_ena, data_bus, data_bus);
alu0 : ALU port map(prim_clk, data_bus, alu_acc);
acc : accumulator port map(prim_clk, alu_acc, acc_set, acc_ena, data_bus);
end behaviour;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Control_Unit is
port( sys_clk, clk_s, clk_e : in std_logic;
acc_ena, acc_set, pc_set, pc_ena: out std_logic;
stepp : out std_logic_vector(5 downto 0)); --just to ko
end Control_Unit;
architecture behaviour of Control_Unit is
signal step : std_logic_vector(5 downto 0);
component Stepper
port( clk : in std_logic;
step : out std_logic_vector(5 downto 0));
end component;
begin
stpr : Stepper port map(sys_clk, step);
stepp <= step;
process(sys_clk, step)
begin
if rising_edge(sys_clk) then
if step(0) = '1' then
case clk_s is
when '1' =>
acc_set <= '1';
when '0' =>
acc_set <= '0';
end case;
case clk_e is
when '1' =>
pc_ena <= '1';
when '0' =>
pc_ena <= '0';
end case;
elsif step(1) = '1' then
case clk_s is
when '1' =>
null;
when '0' =>
null;
end case;
case clk_e is
when '1' =>
null;
when '0' =>
null;
end case;
elsif step(2) = '1' then
case clk_s is
when '1' =>
pc_set <= '1';
when '0' =>
pc_set <= '0';
end case;
case clk_e is
when '1' =>
acc_ena <= '1';
when '0' =>
acc_ena <= '0';
end case;
end if;
end if;
end process;
end behaviour;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY ALU IS
port( clk: in std_logic;
d1: in std_logic_vector(15 downto 0);
d3 : out std_logic_vector(15 downto 0));
END ALU;
ARCHITECTURE behaviour OF ALU IS
signal Zsig: signed(15 downto 0);
begin
process(clk, d1)
begin
if rising_edge(clk) then
Zsig <= signed(d1) + 1;
end if;
end process;
d3 <= std_logic_vector(signed(Zsig));
end behaviour;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity Clock is
port( clk :in std_logic;
clk_s : out std_logic;
clk_e : out std_logic);
end Clock;
--slowing down the clock so I can track data flow.
architecture Behavioral of Clock is
signal count: integer := 1;
signal clock_1: std_logic := '1';
signal clock_2: std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
count <= count + 1;
if count = 12500000 then --10
clock_1 <= not clock_1;
count <= 1;
elsif count = 5000000 then--4
clock_2 <= not clock_2;
end if;
end if;
end process;
clk_e <= clock_1 or clock_2;
clk_s <= clock_1 and clock_2;
end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
entity stepper is
port (clk : in std_logic;
step: out std_logic_vector(5 downto 0));
end stepper;
architecture behav of stepper is
signal count : integer := 0;
begin
Process(clk)
begin
if rising_edge(clk) then
count <= count+1;
if count = 0 then --0
step <= "000001";
elsif count = 23750000 then --19
step <= "000010";
elsif count = 48750000 then --39
step <= "000100";
elsif count = 73750000 then --59
step <= "001000";
elsif count = 98750000 then --79
step <= "010000";
elsif count = 123750000 then --99
step <= "100000";
elsif count = 148750000 then --119
count <= 0;
end if;
end if;
end Process;
end behav;
library IEEE;
use ieee.std_logic_1164.all;
entity program_Counter is
port( clk: in std_logic;
set, en : in std_logic;
pc_in : in std_logic_vector(15 downto 0);
pc_out : out std_logic_vector(15 downto 0));
end program_Counter;
Architecture behaviour of program_Counter is
signal RAM : std_logic_vector(15 downto 0);
begin
process(clk, RAM, set, en)
begin
if rising_edge(clk) then
if set = '1' then
RAM <= pc_in;
elsif en = '1' then
pc_out <= RAM;
else
pc_out <= "ZZZZZZZZZZZZZZZZ";
end if;
end if;
end process;
end behaviour;
library IEEE;
use ieee.std_logic_1164.all;
entity accumulator is
port( clk: in std_logic;
frm_ALU: in std_logic_vector(15 downto 0);
acc_set, acc_ena : in std_logic;
to_bus : out std_logic_vector(15 downto 0));
end accumulator;
Architecture behaviour of accumulator is
signal RAM : std_logic_vector(15 downto 0);
begin
process(clk, acc_set, acc_ena, RAM)
begin
if rising_edge(clk) then
if acc_set = '1' then
RAM <= frm_ALU;
elsif acc_ena = '1' then
to_bus <= RAM;
else
to_bus <= "ZZZZZZZZZZZZZZZZ";
end if;
end if;
end process;
end behaviour;
Sorry for what must be riddled with coding taboos. I feel I should point out that when I originally wrote the code it ran fine with an ADD instruction, I changed it to increment for simplification and didn't run into any problems that I can remember. Several additions later I start getting this error so I strip everything else down to bare bones, removing registers and such but here the error still is.
I use the Quartus II 13.0 software to code and an Altera DE2 EP2C35F672C6 to run the code. Thank you.
I found the problem, after preloading the program counter with the value for 5 and not immediately running into the error when it tried to increment 6 to 7 but instead at 11 it became clear that the logic was not the culprit. The steppers first stage lasts a little shorter than the others(1250000 ticks to be exact) and it desyncs after 6 cycles, after a few more cycles it syncs up again, runs correctly and desyncs again after 6 more. This has been resolved and the counter now increments endlessly, as desired.
I am having problems with drawing the area which is between two curves f(X)=-(x-2)^2+4 and g(x)=x/x+1 which says that the area is in the FIRST quadrant.
Then to calculate the area of the area.Here is my code in wolfram mathematica.
f[x_] = -(x - 2)^2 + 4;
g[x_] = x/x + 1;
Plot[f[x] - g[x], {x, , }]
Integrate[f[x]-g[x],{x,,}]
.Thank you
f[x_] := -(x - 2)^2 + 4
g[x_] := x/x + 1
Plot[{f[x], g[x]}, {x, -1 , 5}]
sol = NSolve[f[x] == g[x], x]
{{x -> 0.585786}, {x -> 3.41421}}
{a, b} = x /. sol
{0.585786, 3.41421}
Integrate[f[x] - g[x], {x, a, b}]
3.77124
First I typed:
-(x - 2)^2 + 4 = x/(x+1)
to find out where they meet.
Then:
area inside the curves y = -(x - 2)^2 + 4 and y = x/(x+1) for x from 0 to 3/2 + sqrt(21)/2
The g[x_] := x/x + 1 function looks odd.
Given the precedence rules, x/x will simplify to 1, and x/x + 1 will thus have constant value 2 (i.e. 1+1).
Did you mean
g[x_] := x/(x+1)
instead ?
To display the surface between the two curves, you can use the Filling option for the Plot function :
Plot[{f[x], g[x]}, {x, -1, 5}, Filling -> {1 -> {2}}]
With the modified g[x_] function above this gives
Area between two curves
In:
Clear[f, g, k]
f[x_] := -(x - 2)^2 + 4
g[x_] := x/x + 1
k[x_] := f[x] - g[x]
roots = x /. Solve[f[x] == g[x], {x}];
RegionMeasure[{x, k[x]}, {{x, First[roots], Last[roots]}}]
Out:
1/2 (6 Sqrt[2] + ArcSinh[2 Sqrt[2]])
We have a binary number and we need to generate combination of 2 1's from the given number. If given such a combination of 2 1's we should be able to produce the next combination.
Example:-
Given vector : 10101111 Given combination : 10100000 output : 10001000
Given vector : 10101111 Given combination : 10001000 output : 10000100
Given vector : 10101111 Given combination : 10000010 output : 10000001
Given vector : 10101111 Given combination : 10000001 output : 00101000
Given vector : 10101111 Given combination : 00101000 output : 00100100
Edit:
Once the 2nd 1 reaches the last 1 in the given binary number, the 1st 1 is incremented(set to next '1' in the binary number and the 2nd '1' is made the '1' that comes after the 1st '1'(as in eg 4))
This is to be done in hardware so it should not be computationally complex. How can we design this module in VHDL.
Here is some asynchronous code that will do the job:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity nex2ones is
Port ( vector : in STD_LOGIC_VECTOR (1 to 8);
combo1 : in STD_LOGIC_VECTOR (1 to 8);
combo2 : out STD_LOGIC_VECTOR (1 to 8);
error : out STD_LOGIC);
end nex2ones;
architecture Behavioral of nex2ones is
type int_array_8 is array (1 to 8) of integer range 0 to 8;
begin
process (vector,combo1)
variable ones_ixs : int_array_8;
variable first_combo1_ix : integer range 0 to 8 := 0;
variable second_combo1_ix: integer range 0 to 8 := 0;
variable first_combo1_k : integer range 0 to 9 := 0;
variable second_combo1_k : integer range 0 to 9 := 0;
variable k : integer range 1 to 9;
begin
ones_ixs := (others => 0); -- indices of 1s in vector
combo2 <= (others => '0');
k := 1;
first_combo1_ix := 0;
second_combo1_ix := 0;
first_combo1_k := 0; -- corresponding ptr to ones_ixs
second_combo1_k := 0;
error <= '0';
for j in 1 to 8 loop
if combo1(j) = '1' then
if first_combo1_ix = 0 then
first_combo1_ix := j;
first_combo1_k := k;
else
second_combo1_ix := j;
second_combo1_k := k;
end if;
end if;
if vector(j) = '1' then
ones_ixs(k) := j;
k := k + 1;
end if;
end loop;
if k > 1 then k := k - 1; end if; -- point to last nonzero index
if (first_combo1_ix = 0 or second_combo1_ix = 0)
--or (first_combo1_ix = ones_ixs(k-1) and second_combo1_ix = ones_ixs(k))
or (k < 2) then
error <= '1';
else -- no error proceed
if second_combo1_ix = ones_ixs(k) then -- can't slide 2nd anymore
if (second_combo1_k - first_combo1_k) > 1 then -- is 1st movable
combo2(ones_ixs(first_combo1_k + 1)) <= '1'; -- move 1st
if (second_combo1_k - first_combo1_k) > 2 then -- is 2nd movable
combo2(ones_ixs(first_combo1_k + 2)) <= '1'; -- move 2nd
else
combo2(ones_ixs(second_combo1_k)) <= '1'; -- leave 2nd be
end if;
else
error <= '1'; -- no mas
end if;
else
combo2(ones_ixs(first_combo1_k)) <= '1'; -- leave 1st be
combo2(ones_ixs(second_combo1_k + 1)) <= '1'; -- next
end if;
end if;
end process;
end Behavioral;
Testbench output:
ps vector combo1 combo2
error
0 00000000 00000000 00000000 1
100000 10101111 10100000 10001000 0
200000 10101111 10001000 10000100 0
300000 10101111 10000010 10000001 0
400000 10101111 10000001 00101000 0
500000 10101111 00101000 00100100 0
600000 10101111 00100100 00100010 0
700000 10101111 00000011 00000000 1
800000 11001110 00000110 00000000 1
900000 10001110 00001010 00000110 0
1000000 11001110 00001010 00000110 0
this is my first question. Sorry my english.
I have a classes like this:
TSFis_S = class(TPersistent)
private
_SFis_MID : Integer;
public
property SFis_MID : Integer read _SFis_MID write _SFis_MID;
end;
TSFis_D = class(TPersistent)
private
_SFis_MID : Integer;
_SFis_S : TObjectList<TSFis_S>;
public
property SFis_MID : Integer read _SFis_MID write _SFis_MID;
property SFis_S : TObjectList<TSFis_S> read _SFis_S write _SFis_S;
end;
TSFis_M = class(TPersistent)
private
_SFis_MID : Integer;
_SFis_D : TObjectList<TSFis_D>;
public
property SFis_MID : Integer read _SFis_MID write _SFis_MID;
property SFis_D : TObjectList<TSFis_D> read _SFis_D write _SFis_D;
function ToJSON:TJSONValue;
destructor Destroy;
end;
I trying convert TSFis_M Object to JSon and Revert to Object for my datasnap application. I use converts and reverters for my datatypes (TObjectList and TObjectList)
{ TSFis_M }
function JSonToSFis_M(json: TJSONValue): TSFis_M;
var
UnMarshaller: TJSONUnMarshal;
begin
if json is TJSONNull then
exit(nil);
UnMarshaller := TJSONUnMarshal.Create;
try
UnMarshaller.RegisterReverter(TSFis_M, '_FisTar',
procedure(Data: TObject; Field: string; Arg: string)
var
ctx: TRttiContext;
datetime :
TDateTime;
begin
datetime := EncodeDateTime(StrToInt(Copy(Arg, 7, 4)), StrToInt(Copy(Arg, 4, 2)), StrToInt(Copy(Arg, 1, 2)), StrToInt
(Copy(Arg, 12, 2)), StrToInt(Copy(Arg, 15, 2)), StrToInt(Copy(Arg, 18, 2)), 0);
ctx.GetType(Data.ClassType).GetField(Field).SetValue(Data, datetime);
end
);
UnMarshaller.RegisterReverter(TSFis_D, '_SFis_S',
procedure(Data: TObject; Field: String; Args: TListOfObjects)
var
obj: TObject;
SFisS: TObjectList<TSFis_S>;
SFis, SFisNew: TSFis_S;
begin
if TSFis_D(Data)._SFis_S=Nil
then TSFis_D(Data)._SFis_S := TObjectList<TSFis_S>.Create(True);
SFisS := TSFis_D(Data)._SFis_S;
SFisS.Clear;
for obj in Args do
begin
SFis := obj as TSFis_S;
SFisNew := TSFis_S.Create;
SFisS.Add(SFisNew);
SFisNew._SFis_MID := SFis._SFis_MID;
end;
end
);
UnMarshaller.RegisterReverter(TSFis_M, '_SFis_D',
procedure(Data: TObject; Field: String; Args: TListOfObjects)
var
obj: TObject;
SFisD: TObjectList<TSFis_D>;
SFis, SFisNew: TSFis_D;
i: integer;
begin
if TSFis_M(Data)._SFis_D=Nil then
TSFis_M(Data)._SFis_D := TObjectList<TSFis_D>.Create(True);
SFisD := TSFis_M(Data)._SFis_D;
SFisD.Clear;
for obj in Args do
begin
SFis := obj as TSFis_D;
SFisNew := TSFis_D.Create;
SFisD.Add(SFisNew);
SFisNew._SFis_MID := SFis._SFis_MID;
end;
end
);
exit(Unmarshaller.Unmarshal(json) as TSFis_M)
finally
UnMarshaller.Free;
end;
end;
function TSFis_M.ToJSON: TJSONValue;
var
Marshaller: TJSONMarshal;
begin
if Assigned(Self) then
begin
Marshaller := TJSONMarshal.Create(TJSONConverter.Create);
try
Marshaller.RegisterConverter(TSFis_M, '_SFis_D',
function(Data: TObject; Field: String): TListOfObjects
var
FisD: TObjectList<TSFis_D>;
i: integer;
begin
FisD := TSFis_M(Data)._SFis_D;
SetLength(Result, FisD.Count);
if FisD.Count > 0 then
for I := 0 to FisD.Count - 1 do
Result[I] := FisD[i];
end);
Marshaller.RegisterConverter(TSFis_M, '_FisTar',
function(Data: TObject; Field: string): string
var
ctx: TRttiContext; date : TDateTime;
begin
date := ctx.GetType(Data.ClassType).GetField(Field).GetValue(Data).AsType<TDateTime>;
Result := FormatDateTime('dd.mm.yyyy hh:nn:ss', date);
end);
Marshaller.RegisterConverter(TSFis_D, '_SFis_S',
function(Data: TObject; Field: String): TListOfObjects
var
FisD: TObjectList<TSFis_S>;
i: integer;
begin
FisD := TSFis_D(Data)._SFis_S;
SetLength(Result, FisD.Count);
if FisD.Count > 0 then
for I := 0 to FisD.Count - 1 do
Result[I] := FisD[i];
end);
exit(Marshaller.Marshal(Self))
finally
Marshaller.Free;
end;
end
else
exit(TJSONNull.Create);
end;
And finally
for example i put 1 Button and 2 Memo on the form. And i try My created Object convert to Json, Json.ToString to Memo1. And Convert that JSonValue to Object.
procedure TForm1.Button1Click(Sender: TObject);
var
MainFis : TSFis_M;
MainFis2 : TSFis_M;
DFis : TSFis_D;
SFis : TSFis_S;
begin
MainFis := TSFis_M.Create;
MainFis.SFis_D := TObjectList<TSFis_D>.Create(True);
DFis := TSFis_D.Create;
DFis._SFis_MID := 1;
MainFis.SFis_D.Add(DFis);
SFis := TSFis_S.Create;
SFis._SFis_MID := 1;
DFis.SFis_S := TObjectList<TSFis_S>.Create(True);
DFis.SFis_S.Add(SFis);
Memo1.Text := MainFis.ToJSON.ToString;
Edit1.Text := IntToStr(MainFis.SFis_D[0].SFis_S.Count);
MainFis2 := JSonToSFis_M(MainFis.ToJSON);
Edit2.Text := IntToStr(MainFis2.SFis_D[0].SFis_S.Count); // Access violation. Because MainFis2.SFis_D[0].SFis_S = Nil Now (That's the my problem. Why?)
Memo2.Text := MainFis2.ToJSon.ToString;
end;
But when i do this. TSFis_S is disappearing. In first step (ObjectToJSon) no problem.
{"type":"Unit1.TSFis_M","id":1,"fields":
{"_SFis_MID":0,"_SFis_D":
[ {"type":"Unit1.TSFis_D","id":2,"fields":
{"_SFis_MID":1,"_SFis_S":
[ {"type":"Unit1.TSFis_S","id":3,"fields":{"_SFis_MID":1} } ]
}
} ]
}
}
But when i trying revert to Object reverter goes wrong.
I can't found problem. What's my fault.
Thanks
PS: If i didn't explain, sample code here: http://goo.gl/3QnSw