I have just started to work on this workbench for stellaris 6965. My task is to convert a 5V analog input to digital and light up an LED.
Please tell me how to do it!
The first thing that needs to be done is to read the analog input and obtain the digital value (which will be memorized into one of the ADC registers).
The value you will receive will range between 0 - 1023 (2^8-1), if you use an 8-bit ADC. The exact register where your value will be memorized depends on the analog pin you have the input voltage.
After that, you can compare the value of the register (I recommend memorizing it into a variable first since it's volatile -> it can change at any moment) and set a threshold for lighting the LED. So, if your value is greater than x (where x is your threshold) you set the digital output pin to 1. Otherwise you set it to zero.
The operations described above can be put into the main program loop or in a timer interrupt.
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I am reading a book about MIPS. In that book I found the following figure where D represents data, Clk is the clock. Could somebody explain me this as I am not from Electrical Engineering background (I am from Computer Engineering background). What are the crosses in the data (in figure)?
It is important that flipflops provide a stable output on the clock signal. This is why they have to be stable during the time shortly before the clock signal until the time shorty after the clock signal. In your graph, the lines represent the value of your data, so wether your wire is 1 or 0. As you can see in the graph, on the rising clock edge the value is either 1 or 0, but there is no cross, so it cannot change during that time.
On the clock signal, the value gets passed on to Q, so Q can change, indicated by the cross. Then Q will carry this value as input to a logic and the output of that logic will be passed to D. This is why the value of Q changes before the value of D - it takes time to pass the signal through the logic. After that we want to store the value of D in a fliplop again, which is why the value has to become stable again and connot Change until after the clock Signal. The whole Thing starts over again.
Hope this helps! ;)
I am trying to get started with ROI encoding with the Nvidia Encoder NVENC.
As a first step I am trying to get the Nvidia demos to encode using ROI. I know that the switch -qpDeltaMapFile enables the flag enableExtQPDeltaMap. This allows me to send a file with a qp map that the encoder uses to tweak the values obtained by the rate control algorithm.
However there is absolutely no documentation on the format of this file. I tried to use one value per byte, and one byte per value assuming fixed size macroblocks of 16x16. It doesn't seem to work as I would expect.
Any guidance or references would help a lot.
There was a bug in my code. It actually works almost as I described.
Assume your screen is divided equally in 16x16 blocks, then each value will be added to the qp that the rate control algorithm chose. Each value passed is a signed integer, therefore a negative value will improve the quality while a positive value will decrease it. A value of 0 will stay with whatever the rate control algorithm decided.
Based on this figure, executing the AND instruction would cause these values to be assigned to the signals labeled in blue:
RegWrite = 1
ALUSrc = 0
ALU operation = 0000
MemRead = 0
MemWrite = 0
MemtoReg = 0
PCSrc =0
However, I am a little confused which inputs will be used in the Registers block? Can anyone describe the overall AND procedure in the MIPS datapath?
Starting from after the instruction is read from instruction memory, you need to know that AND is an r-type instruction and thus uses 3 registers. Which register is actually used is based off of the encoded instruction. (An R-Type has 3 5-bit fields, one for each reg.) rs and rt go to Read register 1 and 2, while rd goes to Write register. From there, Read data 1 and 2 (the bits of registers s and t) go to the ALU where a bitwise AND is performed on them. The result of that is written to the write register. I traced the path in your picture (omitting the PC incrementing part). I'm taking a class that uses that exact book this semester. If you look a little ahead, it goes deeper into what is going on. The explanation of the control (blue) lines helps a lot. The mux blocks are multiplexers, that is they allow alternating the output between two inputs. In this case, the ALUSrc mux will use Read data 2 because AND is an r-type. If it were i-type, it would switch to use the data coming from the sign extend, because that would be the immediate. The other mux is to allow either memory from data to be written to the write register or the result of an ALU operation. In this case, it will be the result of an ALU operation.
To imply answer your question about the register block, keep in mind that the inputs to the register block are the addresses of the registers your instruction will be using, the register block then either fetches the data in the registers who's addresses were given or write data at the end on this register.
However one note you have an inconsistency in your mux design MemtoReg and ALUSrc should have opposite values, so unless one of the 2 muxes is upside down (which is not advisable) then there is a mistake with your controller logic.
Hi when i write this piece of code :
module memo(out1);
reg [3:0] mem [2:0] ;
output wire [3:0] out1;
initial
begin
mem[0][3:0]=4'b0000;
mem[1][3:0]=4'b1000;
mem[2][3:0]=4'b1010;
end
assign out1= mem[1];
endmodule
i get the following warnings which make the code unsynthesizable
WARNING:Xst:1780 - Signal mem<2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal mem<1> is used but never assigned. This sourceless signal will be automatically connected to value 1000.
WARNING:Xst:1780 - Signal > is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Why am i getting these warnings ?
Haven't i assigned the values of mem[0] ,mem[1] and mem[2]!?? Thanks for your help!
Your module has no inputs and a single output -- out1. I'm not totally sure what the point of the module is with respect to your larger system, but you're basically initializing mem, but then only using mem[1]. You could equivalently have a module which just assigns out1 to the value 4'b1000 (mem never changes). So yes -- you did initialize the array, but because you didn't use any of the other values the xilinx tools are optimizing your module during synthesis and "trimming the fat." If you were to simulate this module (say in modelsim) you'd see your initializations just fine. Based on your warnings though I'm not sure why you've come to the conclusion that your code is unsynthesizable. It appears to me that you could definitely synthesize it, but that it's just sort of a weird way to assign a single value to 4'b1000.
With regards to using initial begins to store values in block ram (e.g. to make a ROM) that's fine. I've done that several times without issue. A common use for this is to store coefficients in block ram, which are read out later. That stated the way this module is written there's no way to read anything out of mem anyway.
I am trying to understand the diagram for register write operation in MIPS(Single Cycle Data Path). I do not get why do we need to AND the output of the decoder to the write enable signal? I am not getting how would it enable the specific register. Please help me out with it.
Thanks.
There are several inconsistencies in the diagram. The "n-to-2^n" decoder should have n inputs and 2^n outputs. With such a decoder, the number of registers should be 2^n.
The decoder inputs specify the address (i.e. the register) to be written to. For any of the 2^n possible register numbers, the corresponding output of the decoder will be set to 1, with all other outputs set to 0.
The "write" signal is probably driven off a clock.
The purpose of the AND gates is to make the "write" signal propagate to the correct register (just the one!) The register is chosen by the address fed into the decoder, as described above.
The selected register will latch onto the "register data", most probably on the rising edge of the clock. All the remaining registers will keep their present values, since their C inputs will remain at 0 throughout.