I've been looking for the answer quite a while and finally I decided to ask and see if someone here can help me ;)
The format for the conditional jump instruction in MIPS, lets say a beq instruction, contains a 16-bit field that indicates de "size" of the jump. I know it must be added to the current PC in order to obtain the desired direction. My doubt is, how do I set the field for a backwards jump? I guess two's complement? I found this example, but it confused me more than I was... if anyone could explain it briefly I'd be very thankful! By the way, sorry about my grammar/expressions, I'm not very good at english yet.
The example mentioned:
PC+Jump(Forward)
0100 1101 0000 0011 1010 1100 0101 1000
0000 0000 0000 0000 0000 0000 1001 1100
.......................................................................
0100 1101 0000 0011 1010 1100 1111 0100
PC+Jump(Backwards)
0100 1101 0000 0011 1010 1100 0101 1000
1111 1111 1111 1111 1100 0000 1001 1100
.......................................................................
0100 1101 0000 0011 0110 1100 1111 0100
The offset is a signed value, so jumping backward just uses a negative offset.
The examples you've shown demonstrate simple addition. In the context of branching and jumping, the top number represents the current PC, the second number is the offset, and the bottom number is the new PC. Recall that in two's complement, subtraction is the same as addition of a negative number. Notice that in the backward example, the offset is negative. When the offset is encoded in a MIPS instruction, it gets sign-extended to the full 32 bits.
Related
I want to write out the 2s compliment of the hex 0x1234
As I understand the binary would look like: 0001 0010 0011 0100 and decimal 4660
I was under the impression changing the leading 0 indicates positive vs negative, however online calculators aren't giving me any answer so my understanding of this is wrong
Alternatively looking at 0x8001 as an example: the decimal would be 32769 and the binary 1000 0000 0000 0001
Online calculators return an answer of -32767 as the 2s compliment
Could anyone please offer an explanation or some other post that explains in detail this concept of 2s compliment? Thank you very much!
You get a number's two's complement by inverting all bits and then adding one to it. It must be agreed up front how many bits/digits are involved, i.e. what the word size is. For instance, the result will not be the same for 0x1234 and 0x00001234.
For your example (4 hex digits): 0x1234
In binary: 0b0001 0010 0011 0100
Invert bits: 0b1110 1101 1100 1011
Add one: 0b1110 1101 1100 1100
In hex: 0xEDCC
I have been given the hexadecimal number 0xAA and been told to perform the following operations on it, in order:
Shift right by 3
And with 0x18
Shift left by 2
Here are my steps for doing this:
1.) Represent 0xAA in binary
0xAA = 1010 1010
2.) Shift right by 3
0001 0101
3.) Represent 0x18 in binary
0x18 = 0001 1000
4.) Perform 0001 0101 and 0001 1000
0001 0101 & 0001 1000 = 0001 0000
5.) Shift left by 2
0100 0000
And that is my final answer, 0100 0000. However, the answer I am told I should get is 0111. I cannot figure out where I am going wrong, or how I should get that answer. I was hoping someone could tell me where I am going wrong. Thank you all very much.
It seems that I am calculating the correct result, and it is the expected result that is incorrect. Thank you all for your help.
I'm working on this disassembling assignment and a bit confused.
Disassemble the following machine code into operations and arguments,
e.g., ADD R1,R2,R3.Explain what the whole program does,either in plain
English or in C type of pseudo code Note: you need to make up unique
labels for your assembly code.
Add r: Code
0x00: 07 FF
0x02: 06 08
0x04: 28 08
0x06: 38 02
0x08: 02 47
0x0A: 3C 00
here's the simple processor
w - Write back ALU output to register file
src1 - Address for first ALU operand
src2 - Address for second ALU operand
dst - Address in where output is written
Here are the opcodes used in the assignment
ADD 0x0 R[src1] + R[src2]->R[dst]
SUB 0x1 R[src1] – R[src2]->R[dst]
BLEZ 0xA If R[src1] ≤ 0, branch to BAddr (The last 6 bits are the
address)
HALT 0xF
Here's what I got
0000 0111 1111 1111
0000 0110 0000 1000
0001 1000 0000 0008
0011 1000 0000 0001
0000 0001 0010 0111
0011 1110 0000 0000
I get confused here - 0000 0111 1111 1111 looking at the instruction table, it looks like the program is subtracting from the same register and placing the result in the same register. Am I right? I feel like it is wrong. Thanks in advance!
I did not check your opcodes but what you are describing is one way of reseting register to zero. Which makes sense as you do not know what that register contains. Other times XOR operation is used to get the same result.
Hexadecimal in mips: If I have 0x80000000 and I subtract it by 0xD00000000
my answer is 0X -50000000
is this possible in mips having a negative in or is there another way to write this? That is correct?
Remember, if you look at the most significant bit, you'll know if you are working with a negative number. For simplicity, let's just look at the four most significant bits.
0x80 = 1000 0000
0xD0 = 1101 0000
So those values are already negative. You want to subtract them, that is, 0x80 - 0xD0. Well, subtraction is addition (a-b = a + -b), and the whole point of 2's compliment is that you can add signed numbers and get the result you expect. So let's negate 0xD0:
1101 0000 # original value
0010 1111 # flip the bits
0011 0000 # add 1
If that didn't make sense, ask the all-knowing Wikipedia.
Now, we can add the values:
1000 0000
0011 0000
---------
1011 0000
So if I've done it right, 0x80 - 0xD0 = 0xB0. It's still a negative number (but you don't put a minus sign in front of it, it's implied by the MSBit). And that makes sense, because 0x80 is a very negative number, and 0xD0 is a less negative number than 0x80. (Really, it is... 0xFF is -1, the least negative number.)
I'm not sure if I can ask a binary question here but here goes..
We had this question on our midterm but our professor hasn't provided a correct answer for it. It's been driving me crazy and the final is coming soon so it might be a good idea to fill this gap. Thanks!
Find the smallest two's complement number that, when added to 0101 0101 would result in an overflow. Express your answer in binary.
My reasoning:
I found the range of the original binary 0101 0101 by converting it to an actual number and then added one to it. Then I converted the number that was 1 more than the range into 8-bit binary as my answer. However, this only earned me 3/6 marks. I have no idea what else I could've done. Any insights would be greatly appreciated!
The original binary is a positive number (0 sign bit). Overflow occurs when you add a positive number to it that changes the sign bit. It should be easy to see what the smallest number is using binary notation:
No overflow:
0101 0101
+ 0010 1010
---------
0111 1111
Overflow:
0101 0101
+ 0010 1011
---------
1000 0000
I have no idea if this is what your prof was looking for. (You can probably just subtract from 1000 0000 instead of looking at it as a pattern.)
EDIT Since you asked for an example (meaning something different from the above), here's how subtraction would work:
1000 0000 (the target overflow quantity)
- 0101 0101 (the original binary)
---------
0010 1011 (the smallest number that will overflow when added to original)
That number is 85 in decimal, so 128-85 is 43