Is it possible to connect an accelerator with several memory mapped inputs/outputs? - chisel

Question

Again I have some questions that are mainly due to my inexperience.
I am designing a memory mapped accelerator, the idea is that the accelerator will have 1 Data input, 1 Data output, and a control input.
And I want all this connections to be memory mapped and connected via FIFOs.
I have already design a memory mapped accelerator before, but it just had 1 input and 1 output as the example given (GenericFIR).
If we check the example of the GenericFIR example we can see how to connect 1 Input and 1 Output:
// DOC include start: GenericFIRBlock chisel
abstract class GenericFIRBlock[D, U, EO, EI, B<:Data, T<:Data:Ring]
(
genIn: T,
genOut: T,
coeffs: Seq[T]
)(implicit p: Parameters) extends DspBlock[D, U, EO, EI, B] {
val streamNode = AXI4StreamIdentityNode()
val mem = None
lazy val module = new LazyModuleImp(this) {
require(streamNode.in.length == 1)
require(streamNode.out.length == 1)
val in = streamNode.in.head._1
val out = streamNode.out.head._1
// instantiate generic fir
val fir = Module(new GenericFIR(genIn, genOut, coeffs))
// Attach ready and valid to outside interface
in.ready := fir.io.in.ready
fir.io.in.valid := in.valid
fir.io.out.ready := out.ready
out.valid := fir.io.out.valid
// cast UInt to T
fir.io.in.bits := in.bits.data.asTypeOf(GenericFIRBundle(genIn))
// cast T to UInt
out.bits.data := fir.io.out.bits.asUInt
}
}
// DOC include end: GenericFIRBlock chisel
But how do we modify this for the case in which the GenericFIR has two InputBundles and two OutputBundles? Lets say in1, in2, out1, out2 and all of them with their Ready/Valid signals (Decoupled).
Also how do we connect the StreamNodes after?
Thanks!