Configuration from Multiple Architecture - configuration

Question

I am trying to learn Structural Modelling. So in my library code, I have only "AND_gate" entity with 2 architecture. and_3 is my first architecture for 3 input and and_4 is the second architecture for 4 input.
I am trying to use them as components but I have a problem with configuration.
and_4 is analyzed last so AND1 and AND2 work without problem because they are using and_4.
So my problem is when I try to draw RTL Schematic, my project doesn't use AND3 and AND4. I need to configure and_3 architecture for them.
...
architecture Structure of Structural_Modelling is
component AND_gate is
Port ( INA1 : in STD_LOGIC;
INA2 : in STD_LOGIC;
INA3 : in STD_LOGIC;
INA4 : in STD_LOGIC;
OA : out STD_LOGIC);
end component;
for AND3 : AND_gate use entity work.AND_gate(and_3);
for AND4 : AND_gate use entity work.AND_gate(and_3);
signal wire1, wire2, wire3, wire4 : STD_LOGIC;
begin
AND1 : AND_gate port map (nx,y,t,nw,wire1);
AND2 : AND_gate port map (x,y,nt,nw,wire2);
AND3 : AND_gate port map (y,z,w,wire3);
AND4 : AND_gate port map (ny,nz,nw,wire4);
end Structure;
This is my VHDL code for components library:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AND_gate is
Port ( INA1 : in STD_LOGIC;
INA2 : in STD_LOGIC;
INA3 : in STD_LOGIC;
INA4 : in STD_LOGIC;
OA : out STD_LOGIC);
end AND_gate;
architecture and_3 of AND_gate is
begin
OA <= INA1 and INA2 and INA3 ; -- 3 input AND gate
end and_3;
architecture and_4 of AND_gate is
begin
OA <= INA1 and INA2 and INA3 and INA4 ; -- 4 input AND gate
end and_4;

Answer 1

I found out it is not possible to instantiate from multiple architectures of a single entity. Instead of that another entity for the second architecture can be used.