I just started studying computer organization.
My question is similar to this article
How are the address of the memory and that of the register connected?(AddrConstant MIPS instruction)
lw $t0, AddrConstant4($s1)
The meaning of this instruction is $t0=constant 4
How I understand this instruction is adding 4 to the value of register $s1 and, load (4+value of register $s1) into $t0.
My question is that I don't know what value does $s1 already have.
If $s1 has 0, it makes sense.
However, if $s1 has 5, $t0 will have 4+5=9.
who knows what value is in $s1.
or what I understood is wrong?
As soon as I wrote this question, another idea came to me.
AddrConstant4($s1) means put 4 into the value of register $s1. (It doesn't matter what value $s1 had before.)
So lw $t0, AddrConstant4($s1) is same as $t0==4.
This is right?
Its a pseudo instruction, that may expand to two or more instructions.
lw $t0, label($t1)
Expands to something like:
la $at, label
addu $at, $at, $t1
lw $t0, 0($at)
Where la itself is a pseudo instruction involving lui and perhaps ori.
There are some optimizations possible, but for the best code, much better to use la to load the label address into a register for a longer duration, e.g. that can be done outside a loop. (OR change algorithm to use pointers.)
Related
I am confused as to how a Store Word Instruction coming after an LW using the same $rt causes a pipeline stall in MIPS.
Consider this block of code:
lw $s0, 0($t0)
sw $s0, 12($t0)
lw $s1, 4($t0)
sw $s1, 16($t0)
lw $s2, 8($t0)
sw $s2, 20($t0)
Here 3 words are being shifted around in memory. For e.g in the first 2 lines, $s0 is loaded into ,
and then its contents are saved back in the memory. I'm not sure if the sw instruction required $s0 in EX stage or in MEM stage. if it is needed in MEM stage, wouldn't it be resolved just by forwarding without needing to stall the pipeline?
Hypothetically, yes. Forwarding into the MEM stage directly would make it possible to execute dependent LW and SW back-to-back. As long as the loaded word is stored by the SW at least. It wouldn't be possible to have the SW use that loaded word as the base of the address without a pipeline bubble, otherwise it would require forwarding back in time.
But typically you would see a pipeline such as below (source: a model of a 5 stage pipelined MIPS in SIM-PL), with only one forwarder which feeds into EX. With a setup like that, there is no way to forward from LW into SW, the hardware required for it isn't there.
I just have this conceptual question but I can't really find sites that give clear explanation.
But for the temporary register, saved registers and floating point registers, do they contain address of the values we desire or just the values, say 100 or 200?
The answer is both. The register can contain an address when used with a lw instruction like this:
lw $t1, 0($t2) # loads the value at address 0+$t2 into $t1
Other instructions involve registers which contain values:
add $t1, $t2, $t3 # loads value of $t2 + value of $t3 into $t1
If I call the two MIPs instructions
lui $s0, 0x9344 //Load upper immediate
ori $s0, $s0, 0xB01A //Logical Or Immediate
what is the value in $s0? Everytime I work it out I get the value 0x44B01A which I think is wrong.
I need to implement an instruction in MIPS assembly that jumps to a location stored in a register if its value is non-negative; otherwise, it jumps to a location stored in a second register.
I'm having an issue with how to check for negative values in registers and also need help understanding how to implement this.
Suppose you have in $t1 the test register (the one pointing to the address to jump if its contents is non-negative), and in $t2 the register which will hold the address of the jump if $t1 is negative.
Then, this snippet should do the trick:
bge $t1, $zero, is_positive
jr $t2
is_positive:
jr $t1
The first instruction branches to is_positive if $t0 is non-negative. The instruction at that label jumps to the address given by $t1. If the branch is not taken (i.e. $t0 is negative), then the following instruction is executed which will jump to the address given by $t2.
I have the following MIPS code:
addi $s1, $0, 10
lw $t0, 4($s0)
srl $t1, $t0, 1 [STALL becausee $t0 depends on lw's $t0]
add $t2, $t1, $s1 [STALL because $t1 depends on srl's $t1]
sw $t2, 4($s0)
How can I rearrange it to avoid any stalls. I see that all the 2 to 5 line's sequence can't change. We can only move the first line in between srl and add OR lw and srl. Any ideas?
There are 4 read after write (RAW) dependencies in your code: addi->add, lw->srl, srl->add, add->sw. These can't be fixed as you pointed out.
What you can do is move the addi instruction. I would think the best place to move this instruction would be after the lw because in the MIPS architecture all load instructions use a load delay slot. This means that the instruction immediately after the load does not have access to the contents of the load. If you are using this code in a simulator such as spim or MARS this may not be simulated, but assuming you mean to use the loaded value of $t0 in the srl instruction, your assembly above is actually incorrect. For this to work, there should be a nop in between the lw and srl.
For that reason, it would be best to move the addi in between the lw and srl so as to utilize the lw load delay slot.