I've been studying rocket-chip for utilizing diplomacy and I have a decent grasp on the overall structure of how diplomacy works. (I don't understand it totally, but well enough to create some examples on my own). I would like to develop some IP in which the main objective is to have a regmap through the use of a *RegisterRouter.
If I use/modify one of the RegisterNodeExamples from rocket-chip, I get the following:
class MyDeviceController(implicit p: Parameters) extends LazyModule {
val device = new SimpleDevice("my-device", Seq("tutorial,my-device0"))
val node = APBRegisterNode(
//address = Seq(AddressSet(0x10028000, 0xfff)), (Modified since not in APBRegisterNode)
address = AddressSet(0x002000, 0xfff),
//device = device, (Removed since not in APBRegisterNode)
beatBytes = 8)
lazy val module = new LazyModuleImp(this) {
val bigReg = RegInit(0.U(64.W))
val mediumReg = RegInit(0.U(32.W))
val smallReg = RegInit(0.U(16.W))
val tinyReg0 = RegInit(0.U(4.W))
val tinyReg1 = RegInit(0.U(4.W))
node.regmap(
0x00 -> Seq(RegField(64, bigReg)),
0x08 -> Seq(RegField(32, mediumReg)),
0x0C -> Seq(RegField(16, smallReg)),
0x0E -> Seq(
RegField(4, tinyReg0),
RegField(4, tinyReg1)))
}
}
I'm using APB at the moment as I'm very familiar with AMBA protocols and it has the smallest code base under the diplomacy package. And I could make is so either of the AMBA or TL protocols are used later.
My Question
Is there a way to generate verilog just for MyDeviceController as a stand alone component?
I have not been able to figure this out if there is. Obviously if I just try to instantiate MyDeviceController I will get an error for the inward parameters of node not being connected. I'm not sure if you can give a "dummy" node connection? Or if there is some method that can handle that.
Why I want to do this
It is desirable to test the IP standalone in it's own test environment without a full SoC.
My Current Workaround/Solution
To work around this I essentially created a "wrapper" that creates an APBMasterNode and connects to the APBRegisterNode in MyDeviceController.
class APBMaster()(implicit p: Parameters) extends LazyModule {
val apbMasterParameters = APBMasterParameters(
name = "apbMaster"
)
val apbMasterPortParameters = APBMasterPortParameters(
masters = Seq(apbMasterParameters)
)
val node = APBMasterNode(
portParams = Seq(apbMasterPortParameters)
)
lazy val module = new LazyModuleImp(this) {
val io = IO(new Bundle {
val wtf = Output(Bool())
val start = Input(Bool())
})
val myreg = RegInit(0.U(16.W))
myreg := myreg + 1.U
val prdata = Wire(UInt(64.W))
prdata := node.out.head._1.prdata
//seems to need these things to generate the logic
io.wtf := node.out.head._1.pready && !(node.out.head._1.prdata === 0.U)
node.out.head._1.pstrb := 63.U
node.out.head._1.pprot := 0.U
when(myreg(3,0) === 8.U && io.start) {
node.out.head._1.paddr := myreg
node.out.head._1.psel := true.B
node.out.head._1.penable := false.B
node.out.head._1.pwrite := true.B
node.out.head._1.pwdata := myreg + 1.U
} .elsewhen(myreg(3,0) === 9.U) {
node.out.head._1.paddr := myreg
node.out.head._1.psel := true.B
node.out.head._1.penable := true.B
node.out.head._1.pwrite := true.B
node.out.head._1.pwdata := myreg
} otherwise {
node.out.head._1.paddr := 0.U
node.out.head._1.psel := false.B
node.out.head._1.penable := false.B
node.out.head._1.pwrite := false.B
node.out.head._1.pwdata := 0.U
}
}
}
One issue with this, was that I had to create some controls for each of the APB signals. If I did not, the Chisel/FIRRTL compiler/generator would not create any Verilog for MyDeviceController. This is what you see above with the myreg counter being used to do some basic APB transaction.
The wrapper would look like the following:
class APBTop()(implicit p: Parameters) extends LazyModule {
val master = LazyModule(new APBMaster)
val slave = LazyModule(new MyDeviceController()(Parameters.empty))
slave.node := master.node
lazy val module = new LazyModuleImp(this) {
val io = IO(new Bundle {
val busy = Output(Bool())
val wtf = Output(Bool())
val start = Input(Bool())
})
io.busy := true.B
io.wtf := master.module.io.wtf
master.module.io.start := io.start
}
}
I can create this wrapper/master as a typical testing component, then in my testenv just instatiate the MyDeviceController RTL, however I was wondering if there was another solution. It appears that diplomacy is fairly holistic (which I understand why), but was looking for suggestions on how IP level development is tackled for a Diplomatic infrastructure flow.
Thanks
Edit: Update March 2021
It's been a few months and I've spent more time with RocketChip/Chipyard/Diplomacy. This is a better solution, but leaving the old one below.
There is a makeIOs method for several Nodes. Using these we can actually punch out the respective AMBA/TL interface. This allows you to not have to use a wrapper that has nothing but connections.
Here is what it would look like compared to the previous version I suggested
class MyWrapper()(implicit p: Parameters) extends LazyModule {
//val master = LazyModule(new APBMaster)
val ApbPort = APBMasterNode(
portParams = Seq(APBMasterPortParameters(masters = Seq(APBMasterParameters(name = "ApbPort"))))
)
val apbport = InModuleBody {ApbPort.makeIOs()}
This reduces the need for the APBMaster dummy class as well.
Just to have an answer, I ended up using a combination of what myself and Jack Koenig went back and forth on.
If time permits I'll see if there is a way to make a "template" or LazyModule wrapper that does this for testing purposes (for each of the main protocols) and submit it to the Chisel repo.
class APBMaster()(implicit p: Parameters) extends LazyModule {
val apbMasterParameters = APBMasterParameters(
name = "apbMaster"
)
val apbMasterPortParameters = APBMasterPortParameters(
masters = Seq(apbMasterParameters)
)
val node = APBMasterNode(
portParams = Seq(apbMasterPortParameters)
)
lazy val module = new LazyModuleImp(this) {
//The dontTouch here preserves the interface so logic is generated
dontTouch(node.out.head._1)
}
}
class MyWrapper()(implicit p: Parameters) extends LazyModule {
val master = LazyModule(new APBMaster)
val slave = LazyModule(new MySlave()(Parameters.empty))
slave.node := master.node
lazy val module = new LazyModuleImp(this) {
//nothing???
}
}
object MyTestextends App {SSVPllFreqDetect)))
(new ChiselStage).execute(args, Seq(ChiselGeneratorAnnotation(() => LazyModule(new MyWrapper()(Parameters.empty)).module)))
}
Related
I am trying to do the basic tutorial on chisel for verilog generation, I am trying to build a dual port memory:
import chisel3._
import chisel3.stage.ChiselStage
class Memo extends Module {
val io = IO(new Bundle {
val wen = Input(Bool())
val wrAddr = Input(UInt(8.W))
val wrData = Input(UInt(8.W))
val ren = Input(Bool())
val rdAddr = Input(UInt(8.W))
val rdData = Output(UInt(8.W))
})
val mem = Mem(256, UInt(8.W))
when(io.wen) {
mem(io.wrAddr) := io.wrData
}
io.rdData := 0.U
when(io.ren) {
io.rdData := mem(io.rdAddr)
}
}
println((new ChiselStage).emitVerilog(new Memo))
The above code compiles without issues. But I want to hold the rdData value to the old value if ren = 0. For that I commented line io.rdData := 0.U and I got the error:
Errors: 1: in the following tutorials
Tutorial Memo: exception #[:#6.4] : [module Memo] Reference io is not fully initialized.
#[Memo.scala 31:15:#15.6] : io.rdData <= mux(io.ren, mem._T_20.data, VOID) #[Memo.scala 31:15:#15.6]
How do I fix this? How to hold the previous value on rdData? Also what does the Error message mean, that io is not initialized?
The uninitialized error means there are possible simulation paths where the wire io.rdData had never been assigned. If you need to hold onto some value I'd suggest adding a register, something like this.
val mem = Mem(256, UInt(8.W))
when(io.wen) {
mem(io.wrAddr) := io.wrData
}
val lastValue = RegInit(0.U(8.W))
io.rdData := 0.U
when(io.ren) {
io.rdData := mem(io.rdAddr)
lastValue := io.rdData
}.otherwise {
io.rdData := lastValue
}
I'm using the suggestName API for IO(), for example
class TestModule extends MultiIOModule{
val AXI = IO(new AXIWriteIO(32,32,4)).suggestName("axi")
val S_AXI = IO(Flipped(new AXIWriteIO(32,32,4)))
AXI.AW.suggestName("aw")
AXI <> S_AXI
}
It works with the "axi" part, but not the "aw" part.
The suggestName also does not work inside the bundle definition class:
class AXIAddress(val addrWidthBits: Int, val idBits: Int) extends Bundle {
val id = UInt(idBits.W).suggestName("ID")
//...
}
Any idea?
chisel version is 3.2.0
I chisel3 it is not possible to use suggestName inside Bundles. The names emitted into FIRRTL is the chisel variable name. To get the correct naming of the external ports while still being able to use nested bundles internally to represent the AXI interface I have done something like this:
class AXIAddress extends Bundle {
val addr = UInt(32.W)
val size = UInt(4.W)
val len = UInt(2.W)
}
class AXIMasterIF extends Bundle {
val readAddr = Decoupled(new AXIAddress)
val writeAddr = Decoupled(new AXIAddress)
}
object AXIMasterIF {
def apply(): AXIMasterIF = {
val axi = Wire(new AXIMasterIF)
axi
}
}
class AXIExternalIF extends Bundle {
val AWADDR = Output(UInt(32.W))
val AWVALID = Output(Bool())
val AWREADY = Input(Bool())
val AWSIZE = Output(UInt(4.W))
val AWLEN = Output(UInt(2.W))
val ARADDR = Output(UInt(32.W))
val ARVALID = Output(Bool())
val ARREADY = Input(Bool())
val ARSIZE = Output(UInt(4.W))
val ARLEN = Output(UInt(2.W))
def connect(int: AXIMasterIF): Unit = {
this.AWADDR := int.writeAddr.bits.addr
this.AWVALID := int.writeAddr.valid
int.writeAddr.ready := this.AWREADY
this.AWSIZE := int.writeAddr.bits.size
this.AWLEN := int.writeAddr.bits.len
this.ARADDR := int.readAddr.bits.addr
this.ARVALID := int.readAddr.valid
int.readAddr.ready := this.ARREADY
this.ARSIZE := int.readAddr.bits.size
this.ARLEN := int.readAddr.bits.len
}
}
class TopWrapper extends MultiIOModule {
// First instantive the "internal", nested, representation of the AXI Slave interface
val axiInt = AXIMasterIF()
// Then instantiate the external, correctly named, AXI Slave interace that we can connect in Vivado
val axiExt = IO(new AXIExternalIF).suggestName("MM_AXI_0")
// Make connections
axiExt.connect(axiInt)
}
The AXIExternalIF is the one that is exposed to the rest of the system. It must be in the top level module of your design. AXIMasterIF which uses AXIAddres is connected to that interface and is used internally to connect things to the AXI interface.
If you wanna play around with it and look at the emitted verilog you can do that at Scastie
I have a Vec[Decoupled[UInt]] that I want to connect to a Vec of Vec[Decoupled[UInt]] based on a select signal. However, once it seems the directionality of the Decoupled is lost once it is nested two layers deep, so it won't let me initialize the ready signals or drive the output with the input.
For example, Chisel allows me to instantiate this:
class Example extends Module {
val io = IO(new Bundle {
val in = Vec(3, Flipped(Decoupled(UInt(3.W))))
val out = Vec(3, Decoupled(UInt(3.W)))
})
io.in.foreach(_.ready := false.B) // Only here for consistency
io.out <> io.in
}
But this yields an error:
class Example extends Module {
val io = IO(new Bundle {
val sel = Input(UInt(4.W))
val in = Vec(10, Vec(3, Flipped(Decoupled(UInt(3.W)))))
val out = Vec(3, Decoupled(UInt(3.W)))
})
io.in.foreach(_.foreach(_.ready := false.B))
io.out <> io.in(io.sel)
}
The latter gives errors that read
Sink is unwriteable by current module (line 7)
Both left and right are drivers (line 8)
Is this an error with Chisel or am I missing something? How can I work around this?
This is... weird. I haven't found the cause yet but I have confirmed the buggy behavior you are seeing. Fortunately, there is an easy workaround, put the Flipped outside the Vec.
class Example extends Module {
val io = IO(new Bundle {
val sel = Input(UInt(4.W))
val in = Flipped(Vec(10, Vec(3, Decoupled(UInt(3.W)))))
val out = Vec(3, Decoupled(UInt(3.W)))
})
io.in.foreach(_.foreach(_.ready := false.B))
io.out <> io.in(io.sel)
}
I've filed an issue on the Chisel repo to track this bug.
I was following the answer from here: How to do a vector of modules?.
I have a question regrading how to address previus items in the Seq. here is my code:
val ccfLinks = for (j <- 0 until (len - 1)) yield {
val exe_unit = Module(new Ccflink(bitwidth))
if (j == 0) {
// connnect the first stage //
exe_unit.io.i_in := io.i_in
exe_unit.io.q_in := io.q_in
exe_unit.io.coeff_i := coeffs_i(0)
exe_unit.io.coeff_q := coeffs_q(0)
exe_unit.io.pre_i_product := SInt(0)
exe_unit.io.pre_q_product := SInt(0)
} else {
// connect the rest of the chain //
exe_unit.io.i_in := ccfLinks(j-1).io.i_out
exe_unit.io.q_in := ccfLinks(j-1).io.q_out
exe_unit.io.coeff_i := coeffs_i(j)
exe_unit.io.coeff_q := coeffs_q(j)
exe_unit.io.pre_i_product := ccfLinks(j-1).io.i_product
exe_unit.io.pre_q_product := ccfLinks(j-1).io.q_product
}
exe_unit
}
I am trying to connect the current module to the previous, how do I address the previous module ?
trying to compile the code above result in the next error:
"Ccf.scala:240: recursive value ccfLinks needs type [error] exe_unit.io.i_in := ccfLinks(j-1).io.i_out"
Here is fairly straight forward way of doing it. Note the use of foldLeft which takes an head of the list and calls the code thunk with successive pairs. Using more advanced list comprehensions can make this a little more succinct, but I think this is pretty clear what's going on when.
class Element extends Module {
val io = IO(new Bundle {
val in0 = Input(UInt(8.W))
val in1 = Input(UInt(8.W))
val out0 = Output(UInt(8.W))
val out1 = Output(UInt(8.W))
})
val reg0 = RegNext(io.in0, 0.U)
val reg1 = RegNext(io.in1, 0.U)
io.out0 := reg0
io.out1 := reg1
}
/**
* wire together a bunch of elements, into a basic queue
* #param elementCount how big is the queue
*/
class ElementQueue(val elementCount: Int) extends Module {
val io = IO(new Bundle {
val in0 = Input(UInt(8.W))
val in1 = Input(UInt(8.W))
val out0 = Output(UInt(8.W))
val out1 = Output(UInt(8.W))
})
// create a scala Seq of Elements
val elements = Seq.fill(elementCount)(Module(new Element))
// wire the head to the inputs
elements.head.io.in0 := io.in0
elements.head.io.in1 := io.in1
// wire the elements of the queue
val last = elements.tail.foldLeft(elements.head) { case (prior, next) =>
next.io.in0 := prior.io.out0
next.io.in1 := prior.io.out1
next
}
// wire the end of the queue to the outputs
io.out0 := last.io.out0
io.out1 := last.io.out1
}
The following code implements a n N-bit fixed priority arbiter.
import chisel3._
import chisel3.util._
class fixedPriorityArbiter(val n_reqs:Int = 4) extends Module {
val NO_OF_REQS = n_reqs
val io = IO(new Bundle {
val req = Input(UInt(NO_OF_REQS.W))
val grant = Output(UInt(NO_OF_REQS.W))
})
val higherPriReq = Wire(UInt(NO_OF_REQS.W))
higherPriReq := Cat((higherPriReq(NO_OF_REQS-2, 0) | io.req(NO_OF_REQS-2, 0)), UInt(0,1.W))
io.grant := io.req & ~higherPriReq
}
object main_obj extends App {
val DUT = () => new fixedPriorityArbiter()
val margs = Array("--compiler", "verilog")
chisel3.Driver.execute(args= margs, dut= DUT)
}
Inexistent combinatorial loops are reported for this code. The chisel source mirrors a Verilog implementation of the circuit below which doesn't report any combinatorial loops when synthesized in Synopsys Synplify.
The following compile error is reported by FIRRTL in Eclipse IDE on Windows without any Verilog source being generated by FIRRTL
FIRRTL does not support subword analysis so by using a UInt here you are creating what appears to be a combinational loop even though it actually isn't. To get around this, you can use aggregate types like Vecs to make it explicit to Firrtl that you are doing work on the individual bits. Here's an equivalent implementation using a Vec:
class FixedPriorityArbiter(val n_reqs: Int = 4) extends Module {
val NO_OF_REQS = n_reqs
val io = IO(new Bundle {
val req = Input(UInt(NO_OF_REQS.W))
val grant = Output(UInt(NO_OF_REQS.W))
})
val higherPriReq = Wire(Vec(NO_OF_REQS, Bool()))
// Vec implements scala.collection.Seq so you can use such operations as slice and map
val upperOr = higherPriReq.slice(0, NO_OF_REQS-1).zip(io.req(NO_OF_REQS-2, 0).toBools)
.map { case (l, r) => l | r }
higherPriReq := false.B +: upperOr
io.grant := io.req & ~higherPriReq.asUInt
}