how to suggest name inside bundle in chisel3.2? - chisel

Question

I'm using the suggestName API for IO(), for example
class TestModule extends MultiIOModule{
val AXI = IO(new AXIWriteIO(32,32,4)).suggestName("axi")
val S_AXI = IO(Flipped(new AXIWriteIO(32,32,4)))
AXI.AW.suggestName("aw")
AXI <> S_AXI
}
It works with the "axi" part, but not the "aw" part.
The suggestName also does not work inside the bundle definition class:
class AXIAddress(val addrWidthBits: Int, val idBits: Int) extends Bundle {
val id = UInt(idBits.W).suggestName("ID")
//...
}
Any idea?
chisel version is 3.2.0

Answer 1

I chisel3 it is not possible to use suggestName inside Bundles. The names emitted into FIRRTL is the chisel variable name. To get the correct naming of the external ports while still being able to use nested bundles internally to represent the AXI interface I have done something like this:
class AXIAddress extends Bundle {
val addr = UInt(32.W)
val size = UInt(4.W)
val len = UInt(2.W)
}
class AXIMasterIF extends Bundle {
val readAddr = Decoupled(new AXIAddress)
val writeAddr = Decoupled(new AXIAddress)
}
object AXIMasterIF {
def apply(): AXIMasterIF = {
val axi = Wire(new AXIMasterIF)
axi
}
}
class AXIExternalIF extends Bundle {
val AWADDR = Output(UInt(32.W))
val AWVALID = Output(Bool())
val AWREADY = Input(Bool())
val AWSIZE = Output(UInt(4.W))
val AWLEN = Output(UInt(2.W))
val ARADDR = Output(UInt(32.W))
val ARVALID = Output(Bool())
val ARREADY = Input(Bool())
val ARSIZE = Output(UInt(4.W))
val ARLEN = Output(UInt(2.W))
def connect(int: AXIMasterIF): Unit = {
this.AWADDR := int.writeAddr.bits.addr
this.AWVALID := int.writeAddr.valid
int.writeAddr.ready := this.AWREADY
this.AWSIZE := int.writeAddr.bits.size
this.AWLEN := int.writeAddr.bits.len
this.ARADDR := int.readAddr.bits.addr
this.ARVALID := int.readAddr.valid
int.readAddr.ready := this.ARREADY
this.ARSIZE := int.readAddr.bits.size
this.ARLEN := int.readAddr.bits.len
}
}
class TopWrapper extends MultiIOModule {
// First instantive the "internal", nested, representation of the AXI Slave interface
val axiInt = AXIMasterIF()
// Then instantiate the external, correctly named, AXI Slave interace that we can connect in Vivado
val axiExt = IO(new AXIExternalIF).suggestName("MM_AXI_0")
// Make connections
axiExt.connect(axiInt)
}
The AXIExternalIF is the one that is exposed to the rest of the system. It must be in the top level module of your design. AXIMasterIF which uses AXIAddres is connected to that interface and is used internally to connect things to the AXI interface.
If you wanna play around with it and look at the emitted verilog you can do that at Scastie