I am trying to convert the indirect addressing to native MIPS instructions
I already understood how to do it but this is a single choice objective question and two options seems exact same to me
Q) lw $t0, #($t1) # $t0 <- M[M[$t1]]
(A)
lw $t1, 0($t1)
lw $t0, 0($t1)
(B)
lw $t0, 0($t1)
lw $t0, 0($t0)
Both of them seem same to give same result in the end or am I missing something
Related
Here are the MIPS code:
Loop: lw $t0, 0($s1) # $t0=array element
addu $t0, $t0, $s2 # add scalar in $s2
sw $t0, 4($s1) # store result
addi $s1, $s1,–4 # decrement pointer
bne $s1, $zero, Loop # branch $s1!=0
After scheduling, we can pack them like below:
Why addi instruction can move before the sw instruction?
They both use the $s1 register.
Before scheduling in the first iteration,we will get 0($s1)-> $t0, 4($s1)<- $t0+$s2.
However the scheduling result may be 0($s1)-> $t0, 0($s1)<- $t0+$s2
There are obviously different.
What I guess there is a magic in pipeline.
I don't know what the name is,so I call it "anti-data hazard".
Since addi instruction will write back in the 5th stage(WB), we could use the data hazard to make the sw instruction get the old data address($s1) in stage3.
(sw instruction will not trigger forwarding)
Is my guess right?Please tell me.
I am struggling to understand what this block of mips instruction does. I want to find out what the register $t0 has after these instructions.
ori $t0 $zero 0xA5C11000
addi $t1 $zero 0x10010000
sw $t0 ($t1)
lb $t0 1($t1)
sh $t0 2($t1)
lw $t0 ($t1)
I know that the registers $t0 and $t1 have A5C11000 and 10010000 in them. Then the sw command stores $t1 at the location of $t0. Lb then offsets $t1 by 1 and stores that at the location 10010001? I don't know what happens after this.
Not quite: sw stores the contents of $t0 at the address in $t1, i.e. 10010000. lb loads a byte from address $t1 + 1 into $t0. sh stores a halfword (the lower 2 bytes of $t0) at address $t1 +2.
Try stepping through the code in the debugger to see what it does.
have a really basic question here.
Can a register have both a value and an address. As in assuming i want to swap between values: 5 stored in t0 and 7 stored in t1
does this code work:
sw $t0, 0($t0)
sw $t1, 0($t1)
lw $t1, 0 ($t0)
lw $t0, 0 ($t1)
Sorry this might sound stupid
Not really for all values, as sw and lw need proper alignment (valid addresses should be multiple of 4).
That is, your code would only work for values multiple of 4, and anyways it would be a bad idea to do so, because you would be basically write garbage on whichever address you are pointing at.
To swap registers without overwriting a third register you can use the following trick:
xor $t0, $t0, $t1
xor $t1, $t0, $t1
xor $t0, $t0, $t1
I'm very confused about a question in a university past paper. It is as follows:
What is the value in register $s1 after executing the following piece of MIPS
assembly code?
li $t0, 0x1
li $s0, 0x0
li $s1, 0xa5a5a5a5
loop: and $t1, $t0, $s1
beq $t1, $zero, skip
addi $s0, $s0, 1
skip: sll $t0, $t0, 1 # Shift left logical
bne $t0, $zero, loop
(a) 0x10
(b) 0xa5a5a5a5
(c) 0x0
(d) 0x5a5a5a5a
(e) 0x1
The given answer is A - now, as far as I'm aware, the value of $s1 is not changed after its initial declaration - so how is this the case? I'd have thought it would be B?
This shows the QTSpim:
This shows the PCSpim:
Assuming we have something of this sort in MIPS
jal F
F: lw $t1, 0($ra)
lw $t2, 8($ra)
What would we have in $t1 and $t2?
Will $t1 have the instruction code of F??
Say X is the address of label F
when jal is called $ra will hold X
you load what is on $ra to $t1 which is the binary machine laguage of the instruction at X
then you load what is 2 words lower (8) which is here not specified in your code, you need to show a 4th line of code to tell you =)