Say I need to convert the decimal -125 to a signed 8-bit integer, how do I do this?
I’m a computing student and I’m struggling how to figure it out. I understand the basics of converting it to base 2 but I can’t get the answer.
Thanks
A signed 8-bit integer reserves its highest order bit for the sign. 1 indicates the number is negative, 0 indicates the number is positive. Let's start there.
The number you're trying to convert is -125, so the first bit should be 1.
1XXX XXXX
For the next seven bits, we are going to see how many times the number they represent goes into the number we are trying to convert.
The second bit of our number represents 2^6 or 64. We ask how many times 64 can go into 125 and find that the answer is 1.953125.
We cannot represent this number as a 1 or a 0, but we can think about it like this:
64 goes into 125 one time with a remainder of 0.953125 times (or 61)
Let's count the one time in our second bit and use the remainder 61 as our new number.
11XX XXXX
Next is the third bit which represents 2^5 or 32. How many times can 32 go into 61? The answer is not a whole number, but 1.90625 so we follow the logic from the previous step again: using 1 as our third digit and 29 as our new number.
111X XXXX
The fourth bit represents 2^4 or 16 which goes into 29 once with a remainder of 13.
1111 XXXX
The fifth bit represents 2^3 or 8 which goes into 13 once with a remainder of 5.
1111 1XXX
The sixth bit represents 2^2 or 4 which goes into 5 once with a remainder of 1.
1111 11XX
The seventh bit represents 2^1 or 2 which goes into 1 zero times.
1111 110X
The eighth and final bit represents 2^0 or 1 which goes into 1 once.
1111 1101
Thus our 8-bit signed representation of -125 is 11111101.
A "byte" is 8 bits.
A "nibble" (sometimes "nybble") represents 4 bits.
Is there a term to represent a group of 5 bits?
Currently working on a Base32 encoder and need a term to represent a single base32 character, which is represented by 5 bits.
According to sources on Wikipedia, a group of 5 bits has historically been referred to by a variety of names such as a:
pentad
pentade
nickel
nyckle
I was asked the following question on an assignment, but I'm not sure if I did it correctly.
"What is the largest memory space (i.e. program) that can be addressed by processors with the following number of address bits?
(c) 24 bits"
I put 011111111111111111111111 (0 followed by 23 1s). Is this correct? If not, how do I find the answer to this question? You can use a different amount of bits for an example if you want to. Thanks for any help.
No 011111111111111111111111 is not the correct answer. I'm assuming that you were calculating the largest number that can be represented by a signed 24 bit integer.
Memory address would be always unsigned so the answer is the number items that can be represented in 24 bits, which is 2^24 or 1000000000000000000000000 which is 1 followed by 24 zeros (assuming that I counted correctly) - since the address range includes 0 and goes to 1111111111111111111111 (24 1's).
2^N bytes, where N is number of bits in the address space.
For example, the 8088 processor had a 20 bit address space and so it could address 2^20 bytes = 1 MB.
Address space is unsigned so N is full number of bits, not number of bits minus 1.
An address in programming is usually something that represents a location in memory.
You can always represent as many locations as there are unique numbers.
How many locations can you address with a range from 1 to 10? 10.
How many locations can you address with a range from 1 to 2^24? 2^24.
So you can represent 2^24 locations and you didn't answer correctly.
You're on the wrong track.
Memory addresses are unsigned, so the size of the address space is 2^24 bytes, or 16Mb.
If you had 2 bits you could go from 00 to 11, 00, 01, 10, 11, four addresses. Four is 1 with two zeros 0. Two address bits one with two zeros is the number of addresses or 2 to the power 2. 3 bits 0b1000 or 8 addresses 2 to the power 3, 4 bits 0b10000 or 16 addresses, 2 to the power 4 and so on to whatever number of bits you want.
Please have a look at this Single Cycle Data Path in MIPS. The 26 bits of J type instruction are being Bit Extended to 28. I don't get the point. Shouldn't it be extended to 31 so it makes 32 bits overall. Please help me out to clear the concept.
Thanks
This is really no sign extension. Recall that the instructions in MIPS are 4-byte aligned.
This means that you can start an instruction at addresses which are 0 modulus 4 (i.e. 0, 4, 8, 12, ...)
Now, doing a shift left of 2 two bits is like multiplying by 4, which yields numbers which are always 0 modulus 4.
The actual address will be formed with:
- the 4 most significant bits of the nPC (that is PC+4) (lets call them PPPP)
- the 26 bits of the address field specified in the instruction, (lets call them AAA....AA)
- 00 as the two least significant bits (which yields the required instruction alignment)
Thus the address will be (binary) PPPPAAAAAAAAAAAAAAAAAAAAAAAAAA00
I read this:
Recall that paging is implemented by
breaking up an address into a page and
offset number. It is most efficient to
break the address into X page bits and
Y offset bits, rather than perform
arithmetic on the address to calculate
the page number and offset. Because
each bit position represents a power
of 2, splitting an address between
bits results in a page size that is a
power of 2.
I don't quite understand this answer, can anyone give a simpler explanation?
If you are converting a (linear) address to page:offset, you want to divide the address by the page size and take the integer answer as the page, and the reminder as the offset.
This is done using integer division and modulus (MOD, "%") operators in your programming language.
A computer represents an address as a number, stored as binary bits.
Here's an example address: 12 is 1100 in binary.
If the page size is 3, then we'd need to calculate 12/3 and 12%3 to find the page and offset (4:0 respectively).
However, if the page size is 4 (a power of 2), then 4 in binary is 100, and integer division and modulus can be computed using special 'shortcuts': you can strip the last two binary digits to divide, and you can keep only the last two binary digits for modulus. So:
12/4 == 12>>2 (shifting to remove the last two digits)
12%4 == 12&(4-1) (4-1=3 is binary 11, and the '&' (AND) operator only keeps those)
Working with powers of two leads to more efficient hardware so that's what hardware designers do. Consider a cpu with a 32-bit address, and an n-bit page number:
+----------------------+--------------------+
| page number (n bits) | byte offset (32-n) |
+----------------------+--------------------+
This address is sent to the virtual memory unit, which directly separates the page number and byte offset without any arithmetic operations at all. Ie, it treats the 32-bit value as an array of bits, and has (more or less) a wire running directly to each bit. This allows the memory hardware to extract the page number and byte offset in parallel, without performing any arithmetic operations.
At the same time, this approach requires splitting on a bit boundary, which leads directly to power-of-2 page sizes.
If you have n binary digits at your disposal, then you can encode 2n different values.
Given an address, your description states some bits will be used for the page, and some for the offset. As you're using a whole number of binary bits for the for offset Y, then the page size is naturally a power of 2, specifically 2Y.
Because the representation of the data. The page offset sets the size of the page, and since the data is represented in binary, you will have a number n of bits to define the offset, so you will have pages with a size of 2^n.
Let's suppose you have an address like this 10011001, and you split it in 1001:1001 for page:offset. Since you have 4 bits to define the offset, your page's size is 2⁴.
If it is not exact power of 2 then some memory address will be invalid. eg if the page size is 5 byte then to distinguish each byte we need 3 bit in the offset part of the address. Because using 2 bit only 4 byte can be addressed. But using 3 bit offset for 5 byte page keep two address unused. thats why page size should be .......
since all addresses are in binary and are divided into f and d, f=frame no, d=offset. due to be the size in power of 2 a human no need to go for huge mathematical calculation, just by watching the address bits you can identify the f and d. If page size was 2^n the in physical address last n bits represents the offset and remaining bits represent page numbers.
Hopefully this answer will help you.
I realized what I didn't get was how the page sizes are a power of 2. I found out afterwards:
At the smallest level, the page is 1 bit (0 or 1) and the offset is 1 bit (0 or 1). Combining these together, the page size would be 2 x 2 (or 2^2), because of the number of bits they both have (2 each, so 2 x 2).
Now if the page/offset were larger, then it would be n x n -- n being the number of bits they both have.
The page no. is always in the power of 2 as (2^n).
There are several reasons:
1.The memory address is also in 2^n so it will be more easy to move a page.
2.There are two bits which represent the page:
a.Page no. b.Offset no
So,This is also the reason.
3.Memory is in quantised form like charge(q).