Parameter array in SystemVerilog - parameter-passing

Question

In systemverilog, it allows passing parameter array to lower module. Currently I have two .sv modules with parameters that use such feature. Below, lowMod is being instantiated in uppMod.
module lowMod #(parameter logic row [0:2], parameter logic col [0:1])
(output logic a, input logic b);
// main body of codes...
endmodule
and here's the uppMod.
module uppMod #(parameter logic row [0:4], parameter logic col [0:3])
(output logic a, input logic b);
lowMod #(row[1:3], col[0:1]) unit01 (.);
lowMod #(row[1:3], col[2:3]) unit02 (.);
// rest of codes...
endmodule
Constant values are assigned as parameters to the uppMod in testbench, and it works perfectly for behavioural simulation on Modelsim. But when I read it on DC Compiler, complaint pops up
Syntax error at or near token ','. (VER-294)
It complains about the comma when declaring the parameter array. Presumably, I think DC uses VCS-like Verilog simulator (is that right?), and it seems, in contrast to Modelsim, DC doesn't like this syntax.
So is there anyway to make it work? I am actually doing something like this, where these arrays are initialised to some values...
module uppMod #(parameter logic row [0:4] = '{1,1,1}, parameter logic col [0:3] = '{1,1})
(output logic a, input logic b);
lowMod #(row[1:3], col[0:1]) unit01 (.);
lowMod #(row[1:3], col[2:3]) unit02 (.);
// rest of codes...
endmodule
so that when I elaborate the design on DC, my hope is to tune the parameters to the values I want, by
elaborate -library WORK -parameters "row[0:4]=>'{1,2,3,4,5}, col[0:3]=>'{1,2,3,4}"
But that doesn't work either.
Error: Syntax error in parameter value list at or near token '[0:4]' (string position 7). (VER-279)
Any thoughts?
Thanks for your time in advance.
Tidus

Answer 1

DC probably does not support an unpacked array as a parameter. Try making it an packed array of bits. As a packed array, you lose the strict type checking, but it should pass the values

Answer 2

After a few attempts, it seems declaring the parameter logic internally within the module would do the job - simply declare them and initialise them with some values in the lowMod. In uppMod, we also do the same. But because we need to instantiate the lowMod with parametrized values, overriding is required in uppMod, and it works perfectly. In this way, we can avoid the said syntax error for both modules.
Hope this helps. Thanks.