LINT-34 (warning) In design '%s', three-state bus '%s' has non three- state driver '%s' - warnings

Question

I am trying to synthesize a program I created in Verilog using Design Vision.
I get multiple of the following warnings:
Warning: In design 'mergeTOP', three-state bus 'state[0]' has non
three-state driver 'u1/state_reg[0]/Q'. (LINT-34)
Warning: In design 'mergeTOP', three-state bus 'temp_in5[0]' has non
three-state driver 'u1/temp_in05_reg[0]/Q'. (LINT-34)
DESCRIPTION
Synopsys libraries contain descriptions of three-state driving pins on
components. Synopsys tools classify a net as a three-state net if it
is driven by at least one pin that has this three-state attribute.
Normally, if there are multiple drivers on such nets, it is assumed
that all driving pins should be three-state drivers, for correct opera-
tion of the three-state bus. This warning message indicates a situa-
tion where at least one non-three-state driver appears on a three-state
net.
/*======Declarations===============================*/
module controller (clock, reset, start, state, temp_in1, temp_in2, temp_in3, temp_in4, temp_in5, done, temp_out1, temp_out2, temp_out3, temp_out4, temp_out5, out, in);
/*-----------Inputs--------------------------------*/
input clock, reset, start;
input [255:0] in;
input [255:0] temp_out1, temp_out2, temp_out3, temp_out4, temp_out5;
/*-----------Outputs--------------------------------*/
output [5:0] state;
// output [255:0] temp_in01, temp_in02, temp_in03, temp_in04, temp_in05;
output done;
output [255:0] out;
output [255:0] temp_in1, temp_in2, temp_in3, temp_in4, temp_in5;
/*----------------Nets and Registers----------------*/
reg [5:0] state, n_state;
reg [255:0] temp_in01, temp_in02, temp_in03, temp_in04, temp_in05;
reg done;
reg [255:0] out;
always#(posedge clock) // at the posedge of the clock the current state changes based on whether reset is active or the next state determined by the logic.
begin
if (!reset) // if the active low reset is triggered the state is set to 0.
state <= 6'b000000;
else // if reset is high or inactive the current state gets the value of the next state.
state <= n_state;
end
always#* begin // control path
case (state)
6'b000000: begin // state S0, wait for input.
if (start == 1)
n_state = 6'b000001;
else
n_state = 6'b000000;
end
6'b000001: begin // state S1
n_state = 6'b000010;
end
6'b000010: begin // state S2
n_state = 6'b000100;
end
6'b000100: begin // state S3
n_state = 6'b001000;
end
6'b001000: begin // state S4
n_state = 6'b010000;
end
6'b010000: begin // state S5
n_state = 6'b100000;
end
6'b100000: begin // state S5
n_state = 6'b100000;
end
default: n_state = 6'b000000;
endcase
end
always#(posedge clock) begin
if (!reset) begin
temp_in01 <= 0;
out <= 0;
done <= 0;
end
else begin
case(state)
6'b000000: begin
temp_in01 <= in;
out <= in;
done <= 0;
end
6'b000001: begin
temp_in02 <= temp_out1;
out <= temp_out1;
done <= 0;
end
6'b000010: begin
temp_in03 <= temp_out2;
out <= temp_out2;
done <= 0;
end
6'b000100: begin
temp_in04 <= temp_out3;
out <= temp_out3;
done <= 0;
end
6'b001000: begin
temp_in05 <= temp_out4;
out <= temp_out4;
done <= 0;
end
6'b010000: begin
out <= temp_out5;
done <= 0;
end
6'b100000: begin
out <= out;
done <= 1;
end
default: begin
out <= out;
done <= 0;
end
endcase
end
end
assign temp_in5 = temp_in05;
assign temp_in4 = temp_in04;
assign temp_in3 = temp_in03;
assign temp_in2 = temp_in02;
assign temp_in1 = temp_in01;
endmodule
`
/*======Declarations===============================*/
module mergeTOP (clock, reset, start, in, out, done);
/*-----------Inputs--------------------------------*/
input [255:0] in;
input clock, reset, start;
/*-----------Outputs--------------------------------*/
output [255:0] out;
output done;
/*----------------Nets and Registers----------------*/
// reg [255:0] out;
// reg done;
wire [5:0] state;
wire [255:0] temp_out1, temp_out2, temp_out3, temp_out4, temp_out5;
wire [255:0] temp_in1, temp_in2, temp_in3, temp_in4, temp_in5;
controller u1 (.clock(clock), .reset(reset), .start(start), .state(state), .done(done), .out(out), .in(in),
.temp_in1(temp_in1), .temp_in2(temp_in2), .temp_in3(temp_in3), .temp_in4(temp_in4), .temp_in5(temp_in5),
.temp_out1(temp_out1), .temp_out2(temp_out2), .temp_out3(temp_out3), .temp_out4(temp_out4), .temp_out5(temp_out5)
);
merge1 #(16) u2 (.in(temp_in1),.out(temp_out1),.state(state));
merge1 #(32) u3 (.in(temp_in2),.out(temp_out2),.state(state));
merge1 #(64) u4 (.in(temp_in3),.out(temp_out3),.state(state));
merge1 #(128) u5 (.in(temp_in4),.out(temp_out4),.state(state));
merge1 #(256) u6 (.in(temp_in5),.out(temp_out5),.state(state));
endmodule