chisel

chisel

Chisel3: How can I remove Input and Output in Bundle definition

How to declare a variable size memory

How to find the number of PLIC contexts?

what is the idiomatic way to update *part* of a memory element in FIRRTL? this comes up when updating one entry of a line in a cache

Is it possible to connect an accelerator with several memory mapped inputs/outputs?

What are Chisel's Stage and Phase exactly?

How to specify a Blackbox Bundle that maps to `input [127:0]` but acts like a Vec(2, UInt(64)) in the Chisel source?

Implementing a diplomatic AXI Stream interface in Chisel - BundleMap.cloneType error

chisel3 report producing java.lang.NullPointerException

Bundle using Mux

How to write nested fsm in Chisel like SpinalHDL does?

How to not synthesize memory for release in Chisel

chisel Vec() in Bundle class cannot be implemented in Module class

Are chisel3.util.Queue `full` `maybe_full` signals unaccessible external to the queue module?

Generate dynamic bundle

addResource across multiple Chisel Modules while maintaining compile order

Using Parameters to declare variable-sized Vec

Are latches inferred in chisel?

Chisel invert Vec[Bool] one-liner

Debugging module internals in Chisel

Why do poked values change on last clock cycle in chiseltest, thus failing asserts?

Create a generic Bundle in Chisel3

How do I connect a client to an IdentityNode with two managers?

How to add elements in Vec like a binary tree's leaf nodes?

What are these `a.bits.user.amba_prot` signals and why are they only uninitialized conditionally in my HarnessBinder?

Exception connecting Vec of IO

Add a memory to regmap()

Can chisel print time like verilog

suggestName for IO(Vec(...))

Chisel: How the "read" function (or macro) is implemented for the SyncReadMem class?

Chisel function for mux with more than two inputs

Why is ready signal always 0 in arbiter?

Chisel: How to wait for signal assertion in ChiselScalatestTester?

Can I compute constants in software before Chisel begins designing hardware?

Connecting Individual Modules - Chisel

Demuxer : Unconnected Wires / firrtl error

Creating string debug Vec for state machine

Chisel 3.4.2 syncmem and a black box. No memory replacement with --repl-seq-mem option

SyncReadMem generated verilog vs. Rocketchip emitted verilog

Chisel and Timing Constraints files

How to link verilog blackbox to memory of rocketchip in chisel?

How to exchange certain bits of the register

Using chisel3 with namespacing mechanism?

Poking individual bits using peekpoketester

Chisel: getting signal name in final Verilog

How to freely assign values to vec type variables in chisel？

Dumping memory in a VCD file

Chisel/FIRRTL DefnameDifferentPortsException

Use chisel to implement a relatively large-scale project, how to check the progress of done elaborating

How to convert a deprecated low Firrtl Transform to the Dependency API

Accessing regmap RegFields

IP block generation/testing when using diplomacy. Possible to give dummy node?

How to synchronise a bundle between 2 clock domains in chisel

Extending Data Types or way to add information

How to to use the val name of selected element in a chisel Vector in the generated Verilog

Chisel3 REPL Vec assignment into module only works after eval

Chisel3: Vec indexWhere expected Bool, actual Any

Does the Chisel/FIRRTL toolchain do boolean expression optimization?

How to test modules with bundle/vec input?

How to soft reset Chisel Counter

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