Given the MIPS Processor design as seen
I was thinking of adding the sll and srl functions to the processor. I can't seem to have any intuition on how I can retrieve the amounts of zeros to append (shift dynamically from the given shamt from [10:6] of the instruction).
Can anyone give me one headstart on this? Thanks!
The answer is a delayed but I hope that someone in the future will find it helpful.
As you mention the bits in the shamt (shift amount) field are 5 (10 -> 6). So, 2**5=32 which corresponds to the number of bits that can be shifted right/left.
Example:
Assuming that we execute a srl (shift right logical) operation and the value in the shamt field is 00010 (2 in
decimal) and the value in the register we want to shift is
00000000000000000000000000010100
The value becomes shifted by 2 00000000000000000000000000000101
Another example:
Instruction = srl (Shift Right Logical)
Shamt field = 11110 (30 in decimal) Register Value = 11110000000000000000000000000000 Result = 00000000000000000000000000000001
The value in the register gets shifted to the right by 30 bits
indicated by the shamt field and becomes 1.
Depending on the value in the shamt field you shift by N bits the register that needs shifting to the right or to the left; logical or arithmetic.
Related
I'm working with MIPS in Mars. If I'm given the address of an instruction, how do I find the decimal value in the immediate field for the instruction.
i.e. beq $t0, $t1, someLabel - at address (in decimal) 08
This form of branch addressing is called PC-relative addressing. Since all MIPS instructions are 4 bytes long, MIPS stretches the distance of the branch by having PC-relative addressing refer to the number of words to the next instruction instead of the number of bytes. Thus, the 16-bit field can branch four times as far by interpreting the field as a relative word address rather than as a relative byte address. Refer to pic attached. (cred:Computer Organisation and Design David & John)
As we can see the address is 80000 (in decimal). So, in PC relative we get the difference of target and next address /4.
For your question We use
Target (decimal) = (immediate*4)+next instruction (address in decimal)
And your answer is
(Target - next instruction)/4 (this is the third value (immediate field) in the beq statement)
Here's the datapath:
So this seems like a pretty common question but I can't seem to find any answers on how to extend the datapath to implement SLL and SRL.
This is how I would think to do it but I'm not entirely sure:
It would need another mux right next to Read data 1 next to the register file. This mux would take Read data 1 (rs) and Read data 2 (rt) as inputs. It would select Read data 1 if we're not doing a shift operation, and it would select rt if we ARE doing a shift operation (since sll and srl use rt, not rs). This would then be fed into the ALU.
Next, we would need to branch Instruction[10:6] (the shift amount) off of Instruction[15:0], and Instruction[10:6] would then be fed into the other port of the ALU. Is this correct thinking?
This is sll on single cycle datapath, but i am not sure if the ALU now gets 5 instead of 4 bits control input.
If u make sll then the first ALU input would be shamt and the second is the register to be shifted, ALU know if it must make shift because of instruction field, because it is a R-Type instruction. Then the shifted data will be saved in rd register.
SLL SC datapath
You need to modify the datapath for the SLL instruction, adding a input line to the ALU with the "shamt" field in order to determine de shift amount. The ALU will identify the SLL operation by the ALUop field.
Modiffied datapath
You are going in the correct direction. As stated in one of the answers, there can be one additional port added to the ALU which will consider the shamt amount (bits [10:6]). There can be some internal hardware such as a MUX in the ALU which takes care of selecting either the shamt field or Read Data 2 from the output of register file.
Should the shift amount be an immediate value, or a value stored in a register? Does both work?
I've had different websites tell me different things and am confused.
Based on my research the sll (shift left logical) instruction should be used like this:
sll $d, $t, h
Which makes $d = $t shifted left h times.
I've been told that h should be a immediate value, but I was wondering if a register could be used as the third argument, and the value inside that register used as the shift amount. Would that also work?
You are correct.
sll is specific in that it is a R-format instruction where only two registers are used, rd and rs (destination and source), and the shamt field is a immediate value (a constant).
There is another instruction sllv which uses a third register where you specify shift by variable (the register).
Let me clear the point Shift left logical in MIPS 32 bit has following syntax:
SLL destination, Target, Shift amount(Should be immediate value)
Where as in 8086 if we want shift amount more than 1 we have to use a register to store the value of shift amount!
For the following entries, what instructions do they represent respectively?
Binary: 00000001110001011000100000100001
Hexadecimal: 144FFF9D
I'm completely lost on what I'm doing here - searching online has produced a bunch of results that make very little sense to me, but what I've gathered is I'm basically supposed to match up the numbers to their appropriate instructions/registers, but how exactly do I know what those are? Where can I find a comprehensive list? How do I know whether it's an R I or J format function?
The first 6 bits (it is easier to work in binary) are the opcode, from which you can determine how to interpret the rest. This site should get you started: http://www.mrc.uidaho.edu/mrc/people/jff/digital/MIPSir.html
Update: Calling the first 6 bits the opcode is (to be too kind) misleading, but it is enough to tell you how to interpret the rest of the instruction; you may need to look elsewhere (typically at the end of the instruction) for the complete determination of the opcode.
There are 3 Type of MIPS Instructions:
R_type: Opcode must be 000000 (the first 6 bits) and with last 6 bits we can know what is the correct instruction
I_type
j_type
In this case, we have a R-type MIPS instruction and thus :
Opcode rs rt rd shamt funct
000000 01110 00101 10001 00000 100001
addu $s1 , $t6 , $a1
So Im having trouble with a problem. Im givin that a is an array of words and the base address of a is saved in $a0. So for int a[10] find the sum of this array using mips. I really don't know where to start can someone help me start and I think I should be able to finish it. Thanks a bunch!
Since you are given the address of the start of the array, you know that is also your first element. Since this is an array of int, I will assume it means it will use a storage space the size of a word on mips32 which is 4 bytes. Therefore a[1] is located at the address of a[0]+4bytes. A[2] is located at the address of a[0]+8bytes or a[1]+4bytes etc...
From that it follows that all you have to do is just loop 10 times, loading a word each time and adding the value.
The basic flow is:
Let count = 0, sum = 0 (sum is your return value, so $v0)
Load a word value from $a0 into a register
Set $a0 = $a0 + 4 (move from a[count] to a[count+1], integer is 4 bytes on mips32)
Set sum = sum + the register you loaded the word value into
count = count + 1
if count < 10? (set less than, branch) go to #2
jump and link (assuming our sum is already in $v0)
Note: The base address you are given MUST be word-aligned.
Optimization note: You can optimize the number of instructions executed by setting some register to $a0 + 40 before step 1. This means you can get rid of step 5 and step 6 will be a check if $a0 is less than that register you set before step 1. (The last optimization is moving step 4 to step 6's delay slot. If you are using a simulator, this might not be supported though)