So Im having trouble with a problem. Im givin that a is an array of words and the base address of a is saved in $a0. So for int a[10] find the sum of this array using mips. I really don't know where to start can someone help me start and I think I should be able to finish it. Thanks a bunch!
Since you are given the address of the start of the array, you know that is also your first element. Since this is an array of int, I will assume it means it will use a storage space the size of a word on mips32 which is 4 bytes. Therefore a[1] is located at the address of a[0]+4bytes. A[2] is located at the address of a[0]+8bytes or a[1]+4bytes etc...
From that it follows that all you have to do is just loop 10 times, loading a word each time and adding the value.
The basic flow is:
Let count = 0, sum = 0 (sum is your return value, so $v0)
Load a word value from $a0 into a register
Set $a0 = $a0 + 4 (move from a[count] to a[count+1], integer is 4 bytes on mips32)
Set sum = sum + the register you loaded the word value into
count = count + 1
if count < 10? (set less than, branch) go to #2
jump and link (assuming our sum is already in $v0)
Note: The base address you are given MUST be word-aligned.
Optimization note: You can optimize the number of instructions executed by setting some register to $a0 + 40 before step 1. This means you can get rid of step 5 and step 6 will be a check if $a0 is less than that register you set before step 1. (The last optimization is moving step 4 to step 6's delay slot. If you are using a simulator, this might not be supported though)
Related
What happens in the receiving register if I do the following operation
sw $t3,0(t2) ? where t3 and t2 are two already known registers.
Does the value of t2 register get evoked during the operation or does the compiler just uses the default answer to any multiplication by zero which is (0)?
Thanks!
You are missing the '$' before 't2'. For sw and other similar instructions, the number outside of the parenthesis is the offset. For example if the base address of an array is stored in $t2, the value in $t3 will be stored at the 0 offset of that address (the 0 index of the array). Since MIPS is based off of 32-bits, each index in the array that you want to access can be multiplied by 4 to get the correct offset.
I was in an interview and got the following question:
We would like to create a new MIPS command called foo with the following syntax:
foo rt, rs, immediate
Assume that rt and rs are not equal and immediate can be positive, negative or zero with a length of 16 bits.
The command does the following:
rt = immediate
rs = immediate + 4
Answer the following questions:
If we would like to implement this command in single-cycle MIPS, what minimal changes should we do? What if we want in Multi-cycle MIPS?
Create a pseudo-command of the with the basic MIPS commands to create foo.
I thought that the changes should be in the ALU only for both single and multi but I was wrong. I didn't get the opportunity to answer the second question because I blew the first one (I don't know the answer for it). I hope they will give me another chance so now I'm trying to study this material. How can I answer these questions?
For the second question, a pseudo-instruction can given by the following:
ADDI $rt, $0, immediate
ADDI $rs, $rt, 4
First you want to set rt to immediate value, which can be done by adding a zero to the immediate and writing the value back to rt.
Second you need need to add 4 to the immediate and write it back to rs, note that the immediate value is already stored in rt register (by the previous instruction), Now you need to take the value in rt and add an immediate value to it (i.e 4), and write the result back to rs.
Should the shift amount be an immediate value, or a value stored in a register? Does both work?
I've had different websites tell me different things and am confused.
Based on my research the sll (shift left logical) instruction should be used like this:
sll $d, $t, h
Which makes $d = $t shifted left h times.
I've been told that h should be a immediate value, but I was wondering if a register could be used as the third argument, and the value inside that register used as the shift amount. Would that also work?
You are correct.
sll is specific in that it is a R-format instruction where only two registers are used, rd and rs (destination and source), and the shamt field is a immediate value (a constant).
There is another instruction sllv which uses a third register where you specify shift by variable (the register).
Let me clear the point Shift left logical in MIPS 32 bit has following syntax:
SLL destination, Target, Shift amount(Should be immediate value)
Where as in 8086 if we want shift amount more than 1 we have to use a register to store the value of shift amount!
Given the MIPS Processor design as seen
I was thinking of adding the sll and srl functions to the processor. I can't seem to have any intuition on how I can retrieve the amounts of zeros to append (shift dynamically from the given shamt from [10:6] of the instruction).
Can anyone give me one headstart on this? Thanks!
The answer is a delayed but I hope that someone in the future will find it helpful.
As you mention the bits in the shamt (shift amount) field are 5 (10 -> 6). So, 2**5=32 which corresponds to the number of bits that can be shifted right/left.
Example:
Assuming that we execute a srl (shift right logical) operation and the value in the shamt field is 00010 (2 in
decimal) and the value in the register we want to shift is
00000000000000000000000000010100
The value becomes shifted by 2 00000000000000000000000000000101
Another example:
Instruction = srl (Shift Right Logical)
Shamt field = 11110 (30 in decimal) Register Value = 11110000000000000000000000000000 Result = 00000000000000000000000000000001
The value in the register gets shifted to the right by 30 bits
indicated by the shamt field and becomes 1.
Depending on the value in the shamt field you shift by N bits the register that needs shifting to the right or to the left; logical or arithmetic.
I am trying to understand how the verilog branch statement works in an immediate instruction format for the MIPS processor. I am having trouble understanding what the following Verilog code does:
IR is the instruction so IR[31:26] would give the opcode.
reg[31:0] BT = PC + 4 + { 14{IR[15]}, IR[15:0], 2'b0};
I see bits and pieces such as we are updating the program counter and that we are taking the last 16 bits of the instruction to get the immediate address. Then we need a 32 bit word so we extend 16 more zeros.
Why is it PC + 4 instead of just PC?
What is 2'b0?
I have read something about sign extension but don't quite understand what is going on here.
Thanks for all the help!
1: Branch offsets in MIPS are calculated relative to the next instruction (since the instruction after the branch is also executed, as the branch delay slot). Thus, we have to use PC +4 for the base address calculation.
2: Since MIPS uses a bytewise memory addressing system (every byte in memory has a unique address), but uses 32-bit (4-byte) words, the specification requires that each instruction be word-aligned; thus, the last two bits of the address point at the bottom byte of the instruction (0x____00).
IN full, the instruction calculates the branch target address by taking the program counter, adding 4 to account for hte branch delay slot, and then adding the sign extended (because the branch offset could be either positive or negative; this is what the 14{IR[15]} does) offset to the target.
Numbers in Verilog can be represented using number of bits tick format of the following number.
2'b11; // 2 bit binary
3'd3 ; // 3 bit decimal
4'ha ; // 4 bit hex
The format describes the following number, the bit pattern used is not changed by the format. Ie 2'b11 is identical to 2'd3;