I am asked to add the shift left logical instruction to a single cycle datapath. I know I need to feed the SHAMT field to the ALU, but I'm not sure how to do this. I understand the basics of single cycle data paths for R-format, branch, load word, and store word, but I'm not sure how the SLL plays in... Can anyone help explain how a single cycle SLL datapath works?
If this is the wrong form for this post, I'd be much obliged if someone would direct me to the correct site.
You simply need to decode the opcode of the SLL instruction and use it to set the ALUOp input of the ALU to 11. You also need to set the multiplexers to put the source register and the shift amount at the appropriate inputs to the ALU.
Related
Here's the datapath:
So this seems like a pretty common question but I can't seem to find any answers on how to extend the datapath to implement SLL and SRL.
This is how I would think to do it but I'm not entirely sure:
It would need another mux right next to Read data 1 next to the register file. This mux would take Read data 1 (rs) and Read data 2 (rt) as inputs. It would select Read data 1 if we're not doing a shift operation, and it would select rt if we ARE doing a shift operation (since sll and srl use rt, not rs). This would then be fed into the ALU.
Next, we would need to branch Instruction[10:6] (the shift amount) off of Instruction[15:0], and Instruction[10:6] would then be fed into the other port of the ALU. Is this correct thinking?
This is sll on single cycle datapath, but i am not sure if the ALU now gets 5 instead of 4 bits control input.
If u make sll then the first ALU input would be shamt and the second is the register to be shifted, ALU know if it must make shift because of instruction field, because it is a R-Type instruction. Then the shifted data will be saved in rd register.
SLL SC datapath
You need to modify the datapath for the SLL instruction, adding a input line to the ALU with the "shamt" field in order to determine de shift amount. The ALU will identify the SLL operation by the ALUop field.
Modiffied datapath
You are going in the correct direction. As stated in one of the answers, there can be one additional port added to the ALU which will consider the shamt amount (bits [10:6]). There can be some internal hardware such as a MUX in the ALU which takes care of selecting either the shamt field or Read Data 2 from the output of register file.
I wonder if anyone knows if beq looks only at a specific bit (LSB) when branching to lable or does it look at the value of the entire register?
I am trying to implement multiplication routine
register t1 has 5(0x0000 0101) i am loading only a byte.
this instruction:
beq $t1,1, label -does not work for some reason.
when I go through the code step by step (i am using xspim -bare mode) it goes through the instruction and then just go to the next line of code when it should be skipping it because the lsb of $t1 is 1
Thanks !
So I'm going over some old quizzes for my Computer Organization final and I must have missed this lecture or something. I'm decently proficient in programming MIPS, but this problem has me completely stumped. Could someone help me understand this?
The diagram is missing lines connecting the various parts of the processor as well as a multiplexor for determining if the next instruction address is coming from the PC+4 or from a register as in a jr ra instruction.
There needs to be a line from the ALU to the write data portion of the register file. This is for R-Type instructions, as their result will need to be written back to the destination register. Going into the ALU needs to be lines from Read data 1 and Read data 2, this is how the values from the registers make their way into the ALU for R-type instructions.
A couple lines have been added from the instruction memory to the registers, you're missing the one to the Write Register though (this specifies the destination register for R-type instructions).
For the PC, the line going into the adder goes into the other input (the above one). The 4 for the adder is constant, as each instruction address is 4 bytes after the previous one, so unless we're jumping to an address we will be executing the instruction immediately after the current instruction. The line from the PC to the read address is also necessary as the PC specifies which instruction address to find the current instruction at. The line going into the PC comes from either the result of the PC+4 addition or from the register specified in a jr ra instruction.
To handle this decision a multiplexor is needed. Multiplexors have two inputs and one output, so this one will have one input from the PC+4 adder (for regular R-type instructions) and another from Read Data 1 (for jr ra instructions). The input from Read Data 1 should be visualized as a split from the line between Read Data 1 and the ALU. The output will go right back to the PC, as it determines the next instruction to execute.
I think that's everything that's wanted for that question, as the prof specifies that control signals are already generated (the multiplexor is a type of control unit, but I think it's necessary nonetheless). Hope that helps!
I am reverse engineering a C MIPS application, in some places I can see negative offsets in lw opcode, like:
80032910 lw $v0, -4($s4)
Positive offsets usually indicate some kind of structure, where one of the members is being accessed, but what code can lead to a negative offset?
For example, it can be generated if you read the previous value of a pointer, e.g. traversing an array from the end to the beginning
int *myDataEnd;
... code ...
while(*myDataEnd > *(myDataEnd-1))
myDataEnd--;
Referencing the integer pointed by myDataEnd-1 may generate that instruction.
Position independent code uses $gp as a pointer into the middle of a 64K region of global data, so you will often see lw $t0, -nnn($gp) in code. If the depth of a stack frame is unpredictable at compile-time, a frame pointer may be used to mark the start of the stack frame, causing there to be memory references with negative offsets to the frame pointer.
Hand optimized code can also use negative offsets to save reloading an address into a register.
I am trying to add jal functionality to the following but I am stuck with how does it work. I know that it stores the old PC+4 value in the $ra register and then transfers the control to the function which transfers back the control by return $ra but how do I implement it in the hardware?
There are two things you need to do.
Add a mux at the input of the Registers so that the PC+4 value can be selected as the data to be written. With the appropriate control signal this will allow you to write PC+4 as an additional effect of the "jal $ra" instruction.
Implement the return "jr $ra" instruction. You will need to add a mux to the chain of logic that selects the next PC so that "read data 1" from the register file can be selected as the next PC when the instruction is "jr xxx".
We ad a new line that takes the PC+4 and sends it to the "Write Data" input of the register file. We need to add a multiplexer. We also need to make sure the "Write Register" field is set to the address of $RA. Register $RA is register number 31 most of the time.