I'm trying to crash problems in the book 'Computer organization and Design'.
I come across a sequence of instructions in solution of book.
But Qtspim, mips assembler, can't interpret them.
Here is instructions. (book 4th edition, problem 2.14.4 a)
add $t2, $t0, $0
srl $t2, $t2, 11
and $t2, $t2, 0x0000003f
and $t1, $t1, 0xffffffc0
ori $t1, $t1, $t2
Why ori has 3 registers? (I thought it is not r-type instruction)
Why and has 32bit immediate? (I thought instruction itself has 32bit wise.)
Thank you in advance.
The first two instructions look ok, but the following three do not. It's possible that those are typos, or that the author of the book was using a different MIPS assembler which accepts those instructions and converts them into valid ones.
For example:
and $t2,$t2,0x0000003f
=>
lui $t2,0 ; ANDing the upper halfword with 0x0000 would set it to 0
andi $t2,$t2,0x003f
and $t1,$t1,0xffffffc0
=>
andi $t1,$t1,0xffc0 ; ANDing the upper halfword with 0xffff would not change it
ori $t1,$t1,$t2
=>
or $t1,$t1,$t2
Related
I am working with MIPS Assembly in the Mars simulator and I am attempting to set it up so that I can enter any 2-digit number (ex: 24) into the Keyboard and Display MMIO Simulator and then take it from MMIO addresses and put it into my registers for manipulation. This technique will use polling, which I understand to some degree.
I can load individual characters and place their ascii value into my registers using the following code (inside .text):
main:
lui $t0, 0xFFFF #$t0 = 0xFFFF0000
poll: # polling procedure
lw $t1, 0($t0)
andi $t1, $t1, 0x0001
beq $t1, $zero, poll
lw $a0, 4($t0) # load word into register $a0
Is it possible in this case for MMIO to treat the input as an immediate and to take in two at once? If not, then are there any known workarounds to this? Thanks.
Currently I have
lh $t1, 0($t1)
for sign extending $t1 from 16 bit to 32 bits, but this doesn't work. Is there a simple way to sign extend registers in MIPS?
The way I understand your question, even though you had attempted to use lh you actually wanted to sign-extend the halfword value of $t1 rather than the halfword $t1 is pointing to.
You can accomplish this with two shifts:
sll $t1, $t1, 16
sra $t1, $t1, 16
If you started out with 0x8000, you'd get 0x80000000 after the first shift, and 0xffff8000 after the second.
If you started out with 0x7fff, you'd get 0x7fff0000 after the first shift, and 0x7fff after the second.
lh does work but you need to be sure what you're loading from is defined by .half and not .word because of width and little-endian considerations:
main:
la $t5,myhalf
lh $t1,0($t5)
nop
.data
myhalf: .half 0x8000 # this works
# these do _not_
myword: .word 0x80000000
myword2: .word 0x8000
have a really basic question here.
Can a register have both a value and an address. As in assuming i want to swap between values: 5 stored in t0 and 7 stored in t1
does this code work:
sw $t0, 0($t0)
sw $t1, 0($t1)
lw $t1, 0 ($t0)
lw $t0, 0 ($t1)
Sorry this might sound stupid
Not really for all values, as sw and lw need proper alignment (valid addresses should be multiple of 4).
That is, your code would only work for values multiple of 4, and anyways it would be a bad idea to do so, because you would be basically write garbage on whichever address you are pointing at.
To swap registers without overwriting a third register you can use the following trick:
xor $t0, $t0, $t1
xor $t1, $t0, $t1
xor $t0, $t0, $t1
I have the following MIPS code:
addi $s1, $0, 10
lw $t0, 4($s0)
srl $t1, $t0, 1 [STALL becausee $t0 depends on lw's $t0]
add $t2, $t1, $s1 [STALL because $t1 depends on srl's $t1]
sw $t2, 4($s0)
How can I rearrange it to avoid any stalls. I see that all the 2 to 5 line's sequence can't change. We can only move the first line in between srl and add OR lw and srl. Any ideas?
There are 4 read after write (RAW) dependencies in your code: addi->add, lw->srl, srl->add, add->sw. These can't be fixed as you pointed out.
What you can do is move the addi instruction. I would think the best place to move this instruction would be after the lw because in the MIPS architecture all load instructions use a load delay slot. This means that the instruction immediately after the load does not have access to the contents of the load. If you are using this code in a simulator such as spim or MARS this may not be simulated, but assuming you mean to use the loaded value of $t0 in the srl instruction, your assembly above is actually incorrect. For this to work, there should be a nop in between the lw and srl.
For that reason, it would be best to move the addi in between the lw and srl so as to utilize the lw load delay slot.
I am trying to branch to an address:
bne $t0, $0, 0x7813a21c
However, this is incorrect because bne only allocates 16-bits to the immediate
How can I branch to a direct 32-bit address? Is there a way to branch from a value in a register?
You have to use JR to jump to an address stored in a register.
To preform this type of operation you will need a jump statement. You have to tell the code to jump control context to the exact line you wish to specify. This is example syntax: j offset Where in your address is the offset.
Here is a link that better reviews what you have to do. Check out the section on jump. These are the types of jump available. One of them is what you need: j offset, jal offset, jr $rs, jalr $rs
Here is the link:
http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Mips/jump.html
Good luck
We can load 32-bit addresss to the register (e.g. $t1) in 2 steps:
Load the upper 16 bits by lui (Load Upper Immediate).
Load the lower 16 bits by ori (Or Immediate).
NOTE: It is work because lui fills the lower 16 bits with 0s, so bitwise OR load the lower 16 bits (n | 0 = n);
In code below if $t0 is equal to 0 we do skip jr instruction.
Or if $t0 is not equal to 0 we do not skip jr instruction (or we do jump).
beq $t0, $0, SKIP
# load 0x7813a21c to $t0
lui $t1, 0x7813 # load the upper 16 bits
# Now $t1 = 0x78130000
ori $t1, $1, 0xa21c # load the lower 16 bits
# Now $t1 = 0x7813A21C
jr $t1 # as #Matt Eckert said
SKIP: