When does stall take place in this code? - mips

Loop: lw $t2, 0($t1)
add $t3, $t2, $s1
sw $t3, 4($t1)
add $t1, $t1, $t9
bne $t1, $t0, Loop
and $s2, $s4, $s5
I have interpreted that stall takes place in second instruction provided that this loop runs 8 times and we are in third iteration. Can stall take place in any more situation?

Related

Dual-issue scheduling in MIPS

Here are the MIPS code:
Loop: lw $t0, 0($s1) # $t0=array element
addu $t0, $t0, $s2 # add scalar in $s2
sw $t0, 4($s1) # store result
addi $s1, $s1,–4 # decrement pointer
bne $s1, $zero, Loop # branch $s1!=0
After scheduling, we can pack them like below:
Why addi instruction can move before the sw instruction?
They both use the $s1 register.
Before scheduling in the first iteration,we will get 0($s1)-> $t0, 4($s1)<- $t0+$s2.
However the scheduling result may be 0($s1)-> $t0, 0($s1)<- $t0+$s2
There are obviously different.
What I guess there is a magic in pipeline.
I don't know what the name is,so I call it "anti-data hazard".
Since addi instruction will write back in the 5th stage(WB), we could use the data hazard to make the sw instruction get the old data address($s1) in stage3.
(sw instruction will not trigger forwarding)
Is my guess right?Please tell me.

How to change indirect addressing in MIPS?

I am trying to convert the indirect addressing to native MIPS instructions
I already understood how to do it but this is a single choice objective question and two options seems exact same to me
Q) lw $t0, #($t1) # $t0 <- M[M[$t1]]
(A)
lw $t1, 0($t1)
lw $t0, 0($t1)
(B)
lw $t0, 0($t1)
lw $t0, 0($t0)
Both of them seem same to give same result in the end or am I missing something

Little Endian Mips operation

I am struggling to understand what this block of mips instruction does. I want to find out what the register $t0 has after these instructions.
ori $t0 $zero 0xA5C11000
addi $t1 $zero 0x10010000
sw $t0 ($t1)
lb $t0 1($t1)
sh $t0 2($t1)
lw $t0 ($t1)
I know that the registers $t0 and $t1 have A5C11000 and 10010000 in them. Then the sw command stores $t1 at the location of $t0. Lb then offsets $t1 by 1 and stores that at the location 10010001? I don't know what happens after this.
Not quite: sw stores the contents of $t0 at the address in $t1, i.e. 10010000. lb loads a byte from address $t1 + 1 into $t0. sh stores a halfword (the lower 2 bytes of $t0) at address $t1 +2.
Try stepping through the code in the debugger to see what it does.

MIPS Differences among manipulating array address using add, addu, and addi

I am a newcomer to MIPS and I am confused with the following 3 operations when it comes to accessing elements in an array. For example, if I want to change the value of an integer array at index 1 to 6 and right now I only get $s0 for the base address of the array, A[], then what should I do? Code example is like this:
addi $t0, $zero, 4
add $s0, $s0, $t0
addi ($s0), $zero, 6
or
addi $t0, $zero, 4
addu $s0, $s0, $t0
addi ($s0), $zero, 6
or
addi $s0, $s0, 4
addi ($s0), $zero, 6
Could you explain the reason and point out special cases as well.

MIPS Programming in Past Paper

I'm very confused about a question in a university past paper. It is as follows:
What is the value in register $s1 after executing the following piece of MIPS
assembly code?
li $t0, 0x1
li $s0, 0x0
li $s1, 0xa5a5a5a5
loop: and $t1, $t0, $s1
beq $t1, $zero, skip
addi $s0, $s0, 1
skip: sll $t0, $t0, 1 # Shift left logical
bne $t0, $zero, loop
(a) 0x10
(b) 0xa5a5a5a5
(c) 0x0
(d) 0x5a5a5a5a
(e) 0x1
The given answer is A - now, as far as I'm aware, the value of $s1 is not changed after its initial declaration - so how is this the case? I'd have thought it would be B?
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