The code "la $t2 out" must be a code to load address into register $t2, but I am unsure what out means?
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I just started studying computer organization.
My question is similar to this article
How are the address of the memory and that of the register connected?(AddrConstant MIPS instruction)
lw $t0, AddrConstant4($s1)
The meaning of this instruction is $t0=constant 4
How I understand this instruction is adding 4 to the value of register $s1 and, load (4+value of register $s1) into $t0.
My question is that I don't know what value does $s1 already have.
If $s1 has 0, it makes sense.
However, if $s1 has 5, $t0 will have 4+5=9.
who knows what value is in $s1.
or what I understood is wrong?
As soon as I wrote this question, another idea came to me.
AddrConstant4($s1) means put 4 into the value of register $s1. (It doesn't matter what value $s1 had before.)
So lw $t0, AddrConstant4($s1) is same as $t0==4.
This is right?
Its a pseudo instruction, that may expand to two or more instructions.
lw $t0, label($t1)
Expands to something like:
la $at, label
addu $at, $at, $t1
lw $t0, 0($at)
Where la itself is a pseudo instruction involving lui and perhaps ori.
There are some optimizations possible, but for the best code, much better to use la to load the label address into a register for a longer duration, e.g. that can be done outside a loop. (OR change algorithm to use pointers.)
I was trying to let MMIO output display some text like "please enter" before we type input. Can someone help pls?
Read: lui $t0, 0xffff
Loop1: lw $t1, 0($t0)
andi $t1,$t1,0x0001
beq $t1,$zero,Loop1
lw $v0, 4($t0)
jr $ra
Write: lui $t0, 0xffff
la $t2, text
Loop2: lw $t1, 8($t0)
andi $t1,$t1,0x0001
beq $t1,$zero,Loop2
sw $t2, 12($t0)
sw $a0, 12($t0)
jr $ra
Here is my read loop and write loop. In the last part of write loop, "text" is just some random words I hope to display first. This code is not working and whatever I typed, in the output window there's just 1s.
To clear my questions, what I was trying to do is:
mmio output window: text(like enter the character please)
input window: start to input something
I am struggling to understand what this block of mips instruction does. I want to find out what the register $t0 has after these instructions.
ori $t0 $zero 0xA5C11000
addi $t1 $zero 0x10010000
sw $t0 ($t1)
lb $t0 1($t1)
sh $t0 2($t1)
lw $t0 ($t1)
I know that the registers $t0 and $t1 have A5C11000 and 10010000 in them. Then the sw command stores $t1 at the location of $t0. Lb then offsets $t1 by 1 and stores that at the location 10010001? I don't know what happens after this.
Not quite: sw stores the contents of $t0 at the address in $t1, i.e. 10010000. lb loads a byte from address $t1 + 1 into $t0. sh stores a halfword (the lower 2 bytes of $t0) at address $t1 +2.
Try stepping through the code in the debugger to see what it does.
I have the following assembly code disassembled using capstone. I started with entry point obtained from header.
.text : 4195648
...
...
0x400584L lui $t9, 0x40
0x400588L addiu $t9, $t9, 0xba0
0x40058cL jalr $t9
How do I find which address jalr is pointing to? (I thought I could reach main function in C program)
Based on slide number 19 in this reference I made target = 0x0400ba0
I looked for it and found it in .plt section. Here is the disassembly of .plt
.plt : 4197152
...
...
0x400ba0L lui $t7, 0x41
0x400ba4L lw $t9, 0xbe4($t7)
0x400ba8L jr $t9
0x400bacL addiu $t8, $t7, 0xbe4
I am confused - How do I make sense of it. Or how can I reach actual main function in the MIPS disassembly
I have the following MIPS code:
addi $s1, $0, 10
lw $t0, 4($s0)
srl $t1, $t0, 1 [STALL becausee $t0 depends on lw's $t0]
add $t2, $t1, $s1 [STALL because $t1 depends on srl's $t1]
sw $t2, 4($s0)
How can I rearrange it to avoid any stalls. I see that all the 2 to 5 line's sequence can't change. We can only move the first line in between srl and add OR lw and srl. Any ideas?
There are 4 read after write (RAW) dependencies in your code: addi->add, lw->srl, srl->add, add->sw. These can't be fixed as you pointed out.
What you can do is move the addi instruction. I would think the best place to move this instruction would be after the lw because in the MIPS architecture all load instructions use a load delay slot. This means that the instruction immediately after the load does not have access to the contents of the load. If you are using this code in a simulator such as spim or MARS this may not be simulated, but assuming you mean to use the loaded value of $t0 in the srl instruction, your assembly above is actually incorrect. For this to work, there should be a nop in between the lw and srl.
For that reason, it would be best to move the addi in between the lw and srl so as to utilize the lw load delay slot.